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intel? 80331 i/o processor datasheet product features warning: intel corporation products are not intended for use in life support appliances, devices or systems. use of a intel products in such applications without written consent is prohibited. integrated intel xscale ? core ? 500, 667 and 800 mhz ? arm* v5te compliant ? 32 kbyte, 32-way set associative instruction cache with cache locking ? 32 kbyte, 32-way set associative data cache with cache locking. supports write through or write back ? 2 kbyte, 2-way set associative mini-data cache ? 128-entry branch target buffer ? 8-entry write buffer ? 4-entry fill and pend buffer ? performance monitor unit internal bus 266 mhz/64-bit ? 333 mhz on d-0 stepping. pci-x to pci-x bridge ? primary and secondary 133mhz/64-bit pci-x interfaces ? 8k byte data buffers ? four secondary pci output clocks ? secondary bus arbitration ? private device and private memory address translation unit ? 2 kb or 4 kb outbound read queue ? 4 kb outbound write queue ? 4 kb inbound read and write queue ? connects internal bus to pci/x bus a ? messaging unit and expansion rom two programmable 32-bit timers and watchdog timer eight general purpose i/o pins two i 2 c bus interface units memory controller ? pc2700 double data rate (ddr333) sdram ? ddrii 400 sdram ? up to 2 gb of 64-bit ddr333 ? up to 1 gb of 64-bit ddrii400 ? optional single-bit error correction, multi-bit detection support (ecc) ? supports unbuffered or registered dimms and discrete sdram ? 32-bit memory support dma controller ? two independent channels connected to internal bus ? two 1kb queues in ch0 and ch1 ? crc-32c calculation application accelerator unitraid 6 support on d-0 stepping ? performs optional xor on read data ? compute parity across local memory blocks ? 1 kb/512-byte store queue two uart (16550) units ? 64-byte receive and transmit fifos ? 4-pin, master/slave capable peripheral bus interface ? 8-/16-bit data bus with two chip selects interrupt controller unit ? four priority levels ? vector generation ? twelve external interrupt pins with high priority interrupt (hpi#) 829-ball, flip chip ball grid array (fcbga) ? 37.5 mm 2 and 1.27 mm ball pitch document number: 273943-004US august 2005
intel? 80331 i/o processor datasheet 2 august 2005 document number: 273943-004US information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright? intel corporation, 2005 alertview, i960, anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, commerce cart, ct connect, ct media, dialogic, dm3, etherexpress, etox, flashfile, gatherround, i386, i486, icat, icomp, insight960, instantip, intel, intel logo, intel386, i ntel486, intel740, inteldx2, inteldx4, intelsx2, intel chatpad, intel create&share, intel dot.station, intel gigablade, intel inbusiness, intel in side, intel inside logo, intel netburst, intel netstructure, intel play, intel play logo, intel pocket concert, intel singledriver, intel speedstep, intel str ataflash, intel teamstation, intel weboutfitter, intel xeon, intel xscale, itanium, jobanalyst , landesk, lanrover, mcs, mmx, mmx logo, netport, netportexpre ss, optimizer logo, overdrive, paragon, pc dads, pc parents, pentium, pentium ii xeon, pentium iii xeon, performance at your command, proshar e, remoteexpress, screamline, shiva, smartdie, solutions960, sound mark, storageexpress, the computer inside, the journey inside, this way in, tokenexpress, trillium, vivonic, and vtune are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others.
intel? 80331 i/o processor datasheet document number: 273943-004US august 2005 3 contents 1.0 introduction................................................................................................................ ......... 7 1.1 about this document............................................................................................ 7 1.1.1 terminology.............................................................................................. 7 1.1.2 other relevant documents ...................................................................... 8 1.2 about the intel ? 80331 i/o processor ................................................................... 9 2.0 features .................................................................................................................... .......11 2.1 intel xscale ? core ..............................................................................................11 2.2 pci-to-pci bridge unit ........................................................................................11 2.3 address translation unit .....................................................................................12 2.4 memory controller...............................................................................................12 2.5 application accelerator unit ................................................................................12 2.6 peripheral bus interface......................................................................................12 2.7 dma controller....................................................................................................13 2.8 i 2 c bus interface unit..........................................................................................13 2.9 messaging unit....................................................................................................13 2.10 internal bus .........................................................................................................13 2.11 uart units .........................................................................................................13 2.12 interrupt controller unit .......................................................................................14 2.13 gpio ...................................................................................................................14 3.0 package information ........................................................................................................1 5 3.1 functional signal descriptions ............................................................................15 3.2 package thermal specifications .........................................................................52 4.0 electrical specifications................................................................................................... .53 4.1 absolute maximum ratings.................................................................................53 4.2 v ccpll pin requirements ...................................................................................53 4.3 targeted dc specifications.................................................................................54 4.4 targeted ac specifications.................................................................................56 4.4.1 clock signal timings..............................................................................56 4.4.2 ddr/ddr-ii sdram interface signal timings ......................................57 4.4.3 peripheral bus interface signal timings ................................................59 4.4.4 i 2 c interface signal timings...................................................................61 4.4.5 uart interface signal timings ..............................................................61 4.4.6 boundary scan test signal timings ......................................................62 4.5 ac timing waveforms ........................................................................................63 4.6 ac test conditions .............................................................................................67
intel? 80331 i/o processor datasheet 4 august 2005 document number: 273943-004US figures 1 intel ? 80331 i/o processor i/o processor functional block diagram ................ 10 2 829-ball fcbga package diagram .................................................................... 34 3 intel ? 80331 i/o processor ballout (bottom view) .............................................. 35 4 intel ? 80331 i/o processor ballout - left side (bottom view) ............................ 36 5 intel ? 80331 i/o processor ballout - right side (bottom view) .......................... 37 6 clock timing measurement waveforms ............................................................. 63 7 output timing measurement waveforms ........................................................... 63 8 input timing measurement waveforms .............................................................. 64 9i 2 c/smbus interface signal timings ................................................................... 64 10 uart transmitter receiver timing .................................................................... 64 11 ddr sdram write timings ............................................................................... 65 12 ddr sdram read timings ............................................................................... 65 13 write preamble/postamble durations ................................................................ 66 14 ac test load for all signals except pci and ddr sdram .............................. 67 15 ac test load for ddr sdram signals ............................................................. 67 16 pci/pci-x tov(max) rising edge ac test load............................................... 67 17 pci/pci-x tov(max) falling edge ac test load .............................................. 68 18 pci/pci-x tov(min) ac test load .................................................................... 68
intel? 80331 i/o processor datasheet document number: 273943-004US august 2005 5 tables 1 pin description nomenclature.............................................................................15 2 ddr sdram signals..........................................................................................16 4 misc sdram signals.........................................................................................17 3 ddr-ii sdram signals.......................................................................................17 5 peripheral bus interface signals .........................................................................18 6 primary pci bus signals .....................................................................................19 7 secondary pci bus signals ................................................................................21 9i 2 c signals ..........................................................................................................23 8 interrupt signals ..................................................................................................23 10 uart signals......................................................................................................24 11 test and miscellaneous signals..........................................................................26 12 reset strap signals.............................................................................................27 13 power and ground pins ......................................................................................29 14 pin mode behavior ..............................................................................................30 15 pin multiplexing for functional modes.................................................................33 16 fc-style, h-pbga package dimensions ............................................................34 17 829-lead package - alphabetical ball listings ...................................................38 18 829-lead package - alphabetical signal listings ...............................................45 19 absolute maximum ratings.................................................................................53 20 operating conditions...........................................................................................53 21 dc characteristics ..............................................................................................54 22 i cc characteristics ..............................................................................................55 23 pci clock timings...............................................................................................56 24 ddr clock timings .............................................................................................56 25 ddr sdram signal timings ..............................................................................57 26 ddr-ii sdram signal timings...........................................................................58 27 peripheral bus signal timings ............................................................................59 28 pci signal timings..............................................................................................60 29 i 2 c signal timings...............................................................................................61 30 uart signal timings ..........................................................................................61 31 boundary scan test signal timings ...................................................................62 32 ac measurement conditions ..............................................................................67
intel? 80331 i/o processor datasheet 6 august 2005 document number: 273943-004US revision history date revision # description august 2005 004 updated voltages in section 4.3 . march 2005 003 revised: table 14 , modified pin mode behavior for dq[63:32] for 32-bit ddr. table 19 , modified case temperature under bias to 95 o c max table 20 , modified case temperature under bias to 95 o c max table 21 , modified vol1 and voh1 parameters table 23 , added note 4. table 24 , added note 2. table 25 , modified tvb4 and tva4. figure 12 , removed tvb6 parameter. november 2004 002 added d-0 text to product features and body text. revised ball maps and signal designations for intel? 80331 i/o processor design. added icc numbers to table 22 . september 2003 001 initial release.
intel? 80331 i/o processor datasheet introduction document number: 273943-004US august 2005 7 1.0 introduction 1.1 about this document this is the intel ? 80331 i/o processor datasheet . this document contains a functional overview, package signal locations, targeted electrical speci fications, and bus functional waveforms. detailed functional descriptions other than parametric performance are published in the intel ? 80331 i/o processor developer?s manual . intel corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. intel retains the right to make changes to these specifications at any time, without notice. in particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. in fact, this specification does not imply a commitment by intel to design, manufacture, or sell the product described herein. 1.1.1 terminology to aid the discussion of the intel ? 80331 i/o processor (80331) architecture, the following terminology is used: core processor intel xscale ? core within the 80331 local processor intel xscale ? core within the 80331 host processor processor loca ted upstream from the 80331 local bus 80331 internal bus local memory memory subsystem on the intel xscale ? core, memory controller or peripheral bus interface busses. inbound at or toward the internal bus of the 80331 from the pci interface of the atu. outbound at or toward the pci interface of the 80331 atu from the internal bus. downstream at or toward the secondary pci interface from the primary pci interface. upstream at or toward the primary pci interface from the secondary pci interface. qword 64-bit data quantity (8 bytes). dword 32-bit data quantity (4 bytes). word 16-bit data quantity (2 bytes).
intel? 80331 i/o processor datasheet introduction 8 august 2005 document number: 273943-004US 1.1.2 other relevant documents 1. intel xscale ? core developer?s manual (273473), intel corporation. 2. intel ? 80331 i/o processor developer?s manual (273942), intel corporationl. 3. intel ? 80331 i/o processor design guide (273823), intel corporationl. 4. intel ? 80331 i/o processor specification update (273930), intel corporationl. 5. pci-to-pci bridge architecture specification, revision 1.1 - pci special interest group. 6. pci local bus specification , revision 2.3 - pci special interest group. 7. pci-x addendum to the pci local bus specification, revision 1.0a - pci special interest group. 8. pci bus power management interface specification , revision 1.1 - pci special interest group.
intel? 80331 i/o processor datasheet introduction document number: 273943-004US august 2005 9 1.2 about the intel ? 80331 i/o processor the 80331 is a multi-function device that integrates the intel xscale ? core (arm* architecture compliant) with intelligent peripherals and pci-x to pci-x bridge. the 80331 consolidates, into a single system: ? intel xscale ? core. ? pci-to-pci bridge supporting pci-x interfaces on the primary and secondary bus. ? address translation unit (pci-to-internal bus application bridge) interfaced to the secondary bus. ? high-performance memory controller. ? interrupt controller with up to 12 external interrupt inputs. ? two direct memory access (dma) controllers. ? application accelerator. ? messaging unit. ? peripheral bus interface unit. ? two i 2 c bus interface units. ? two 16550 compatible uarts with flow control (four pins). ? eight general purpose input output (gpio) ports. it is an integrated processor that addresses the needs of intelligent i/o applications and helps reduce intelligent i/o system costs.
intel? 80331 i/o processor datasheet introduction 10 august 2005 document number: 273943-004US figure 1 is a functional block diagram of the 80331. figure 1. intel ? 80331 i/o processor i/o processor functional block diagram b2472-02 internal bus primary pci bus secondary pci bus pci-to-pci bridge atu message unit 2 channel dma controller interrupt controller & timers application accelerator arbiter intel xscale ? core bus interface unit 32/64-bit ddr interface memory controller 16-bit pbi brg uart units gpio 2 - 12c units
intel? 80331 i/o processor datasheet features document number: 273943-004US august 2005 11 2.0 features the 80331 combines the intel xscale ? core with powerful new features to create an intelligent i/o processor. this multi-device i/o processor is fully compliant with the pci local bus specification , revision 2.3 and the pci-to-pci bridge architecture specification , revision 1.1. the 80331-specific features include: the subsections that follow briefly ov erview each feature. refer to the intel ? 80331 i/o processor developer?s manual for full technical descriptions. 2.1 intel xscale ? core the 80331 is based upon the intel xscale ? core. the core processor operates at a maximum frequency of 800 mhz. the instruction cache is 32 kbytes in size and is 32-way set associative. also, the core processor includes a data cache that is 32 kbytes and is 32-way set associative, and a mini data cache that is 2 kbytes and is two-way set associative. 2.2 pci-to-pci bridge unit the 80331 provides a pci-x to pci-x bridge un it. the bridge primary and secondary pci-x support 64-bit 133 mhz interfaces compliant to the pci-x addendum to the pci local bus specification , revision 1.0a. ? intel xscale ? core ? application accelerator unit ? address translation unit ? memory controller ? peripheral bus interface ? two i2c bus interface unit s ? pci-x to pci-x bridge with primary and secondary 133 mhz/64-bit pci-x interfaces ? interrupt controller unit ? messaging unit ? internal bus ? two dma controller s ? two uart units ? eight gpio s
intel? 80331 i/o processor datasheet features 12 august 2005 document number: 273943-004US 2.3 address translation unit an address translation unit (atu) allows pci transactions direct access to the 80331 local memory. the atu supports transactions between pci address space and 80331 address space. address translation for the atu is controlled through programmable registers accessible from both the pci interface and the intel xscale ? core. the pci interface of the atu is connected to the 80331 secondary pci interface of the bridge. up stream access to the primary pci interface is controlled by inverse decode with the address windows of the bridge. dual access to registers allows flexibility in mapping the two addr ess spaces. the atu also supports the power management extended capability configuration header that as defined by the pci bus power management interface specification , revision 1.1. 2.4 memory controller the memory controller allows direct control of a ddr sdram memory subsystem. it features programmable chip selects and support for error correction codes (ecc). the memory controller may be configured for ddr sdram at 333 mhz (with 500 mhz and 667 mhz processors) or ddr-ii sdram at 400 mhz (with 500 mhz and 800 mhz processors). the memory controller interface configuration support includes unbuffered dimms, registered dimms, and discrete ddr sdram devices. the memory contoller is dual-ported, with a dedicated interface for the intel xscale ? core bus interface unit and a sec ond interface to the internal bus. external memory may be configured as host addressable memory or private 80331 memory utilizing the address translation unit and bridge. 2.5 application accelerator unit the application accelerator unit (aa) provides low-latency, high-throughput data transfer capability between the aa unit, the 80331 local memory and the pci bus. it executes data transfers from and to the 80331 local memory, from the pci bus to the 80331 local memory, or from the 80331 local memory to the pci bus. the aa unit performs xor operations, computes parity, generates and verifies an eight byte data integrity field, performs memory block fills, and provides the necessary programming interface. the aau has been enhanced to support raid 6 in the d-0 stepping of the 80331. 2.6 peripheral bus interface the peripheral bus interface unit is a data commu nication path to the flash memory components or other peripherals of an 80331 hardware system. the pbi includes support for either 8/16 bit devices. to perform these tasks at high bandwidth , the bus features a burst transfer capability which allows successive 8/16-bit data transfers.
intel? 80331 i/o processor datasheet features document number: 273943-004US august 2005 13 2.7 dma controller the dma controller allows low-latency, high-throughput data transfers between pci bus agents and the local memory. two separate dma channe ls accommodate data transfers to the pci bus. both channels include a local memory to lo cal memory transfer mode. the dma controller supports chaining and unaligned data transfers. it is programmable through the intel xscale ? core only. 2.8 i 2 c bus interface unit the i 2 c (inter-integrated circuit) bus interface unit allows the intel xscale ? core to serve as a master and slave device residing on the i 2 c bus. the i 2 c unit uses a serial bus developed by philips semiconductor*, consisting of a two-pin interface. the bus allows the 80331 to interface to other i 2 c peripherals and microcontrollers for system ma nagement functions. it requires a minimum of hardware components for an economical system to relay status and reliability information on the i/o subsystem to an external device. also refer to i 2 c peripherals for microcontrollers (philips semiconductor). the 80331 includes two i 2 c bus interface units. 2.9 messaging unit the messaging unit (mu) provides data transfer between the pci system and the 80331. it uses interrupts to notify each system when new data ar rives. the mu has four messaging mechanisms: ? message registers ? doorbell registers ? circular queues ? index registers each messaging mechanism allows a host proces sor or external pci device and the 80331 to communicate through message passing and interrupt generation. 2.10 internal bus the internal bus is a high-speed interconn ect between internal units and intel xscale ? core processor. the internal bus operates at 266 mhz and is 64 bits wide. the internal bus on the d-0 stepping of the 80331 operates at 333mhz. 2.11 uart units the 80331 includes two uart units. the uart units allow the intel xscale ? core to serve as a master and slave device residing on the uart bus. the uart units use a serial bus consisting of a four-pin interface. the bus allows the 80331 to in terface to other peripherals and microcontrollers. also refer to 16550 device specification (national semiconductor*).
intel? 80331 i/o processor datasheet features 14 august 2005 document number: 273943-004US 2.12 interrupt controller unit the interrupt controller unit (icu) aggregates inte rrupt sources both external and internal of the 80331 to the intel xscale ? core processor. the icu supports high performance interrupt processing with direct interrupt service routine vector generation on a per source basis. each source has programmability for masking, core processor interrupt input, and priority. 2.13 gpio the 80331 includes eight general purpose i/o (gpi o) pins which can also be used as external interrupt inputs.
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 15 3.0 package information the 80331 is offered in a flip chip ball grid array (fcbga) package. this is a full grid array package with 829 ball connections. 3.1 functional signal descriptions table 1. pin description nomenclature symbol description c configuration i input pin only o output pin only i/o pin may be either an input or output. od open drain pin pwr power pin gnd ground pin - pin must be connected as described. sync(...) synchronous. signal meets timings relative to a clock. sync(p) synchronous to p_clk sync(m) synchronous to m_ck[2:0] sync(s) synchronous to s_clkin sync(t) synchronous to tck async asynchronous. inputs may be asynchronous re lative to all clocks. all asynchronous signals are level-sensitive. rst(p) the pin is reset with p_rst# rst(s) the pin is reset with s_rst# . note that s_rst# is asserted when p_rst# is asserted. rst(m) the pin is reset with m_rst# . note that m_rst# is asserted when p_rst# is asserted or is asserted with software. rst(t) the pin is reset with trst# .
intel? 80331 i/o processor datasheet package information 16 august 2005 document number: 273943-004US table 2. ddr sdram signals name count type description m_ck[2:0] 3o memory clocks are used to provide the positive differential clocks to the external sdram memory subsystem. m_ck[2:0]# 3o memory clocks are used to provide the negative differential clocks to the external sdram memory subsystem. m_rst# 1o async memory reset indicates when the memory subsystem has been reset with p_rst# or a software reset. ma[13:0] 14 o sync(m), rst(m) memory address bus carries the multiplexed row and column addresses to the sdram memory banks. ba[1:0] 2o sync(m), rst(m) sdram bank address indicates which of the sdram internal banks are read or written during the current transaction. ras# 1o sync(m), rst(m) sdram row address strobe indicates the presence of a valid row address on the multiplexed address bus ma[12:0] . cas# 1o sync(m), rst(m) sdram column address strobe indicates the presence of a valid column address on the multiplexed address bus ma[12:0] . we# 1o sync(m), rst(m) sdram write enable indicates that the current memory transaction is a write operation. cs[1:0]# 2o sync(m), rst(m) sdram chip select enables the sdram devices for a memory access (physical banks 0 and 1). cke[1:0] 2o sync(m), rst(m) sdram clock enable enables the clocks for the sdram memory. deasserting will place the sdram in self-refresh mode. dq[63:0] 64 i/o sync(m), rst(m) sdram data bus carries 64-bit data to and from memory. during a data cycle, read or wr ite data is present on one or more contiguous bytes. during write operations, unused pins are driven to determinate values. cb[7:0] 8i/o sync(m), rst(m) sdram ecc check bits carry the 8-bit ecc code to and from memory during data cycles. dqs[8:0] 9i/o sync(m), rst(m) sdram data strobes carry the strobe signals, output in write mode and input in read mode fo r source synchronous data transfer. dm[8:0] 9o sync(m), rst(m) sdram data mask controls which bytes on the data bus should be written. when dm[8:0] is asserted, the sdram devices do not accept valid data from the byte lanes. total 120
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 17 table 3. ddr-ii sdram signals name count type description dqs[8:0]# 9i/o sync(m) rst(m) sdram data strobes carry the differential strobe signals in ddr-ii mode, output in write m ode and input in read mode for source synchronous data transfer. odt[1:0] 2o sync(m) rst(m) on die termination control, turns on sdram termination during writes. ddrres[2:1] 2i/o compensation for ddr ocd (analog) ddr-ii mode only. total 13 table 4. misc sdram signals name count type description ddrcres0 1o analog vss ref pin (analog) both ddrslwcres and ddrimpcres signals connect to this pin through a reference resistor. ddrslwcres 1i/o compensation voltage reference (analog) for ddr driver slew rate control connected through a resistor to ddrcres0 . ddrimpcres 1i/o compensation voltage reference (analog) for ddr driver impedance control connected through a resistor to ddrcres0 . total 3
intel? 80331 i/o processor datasheet package information 18 august 2005 document number: 273943-004US table 5. peripheral bus interface signals name count type description a[22:16] 7o rst(m) address bus 22:16 carries a demultiplexed version of address bits a22:16. during address ( t a ), wait state ( t w ) and data cycles ( t d ) cycles, a22:16 represents the upper seven address bits for the current access. a22:16 allows the pbi interface to address up to 8 mbytes per peripheral device. see ? table 12, ?reset strap signals? on page 27 ? for a functional description. ad[15:0] 16 i/o rst(m) address/data bus carries 16-bit physical addresses and 8-, or 16-bit data to and from memory. during an address ( t a ) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate size ; see below). during a data ( t d ) cycle, bits 0-7, or 0-15 contain read or write data, depending on the corresponding bus width. during write operations to 8-bit wide memory regions, the pbi drives unused bus pi ns high or low. size , which comprises bits 0-1 of the ad lines during a t a cycle, specifies the number of data trans fers during the bus transaction. ad1 ad0 0 0 1 transfer 0 1 2 transfers 1 0 3 transfers 1 1 4 transfers see ? table 12, ?reset strap signals? on page 27 ? for a functional description. a[2:0] 3o rst(m) address bus 2:0 carries a demultiplexed version of bits 2:0 of the ad[15:0] bus. during an address ( t a ) cycle, bits a[2:0] matches ad[2:0] . during a bursted read data ( t d ) cycle, a[2:0] will represent the current byte address in the bursted transaction. a[2:1] are used for an 16-bit wide peripheral while a[1:0] are used for an 8-bit wide peripheral. see ? table 12, ?reset strap signals? on page 27 ? for a functional description. ale 1o rst(m) address latch enable indicates the transfer of a physical address. the pin is asserted during the first address cycle and deasserted during the second address cycle. poe# 1o rst(m) peripheral output enable indicates whether the bus access is a write or a read with respect to the i/o processor and is valid during the entire bus access. this pin may be used to control the oe# input on peripheral devices. 0 = read 1 = write pwe# 1o rst(m) peripheral write enable indicates whether the bus access is a write or a read with respect to the i/o processor and is valid during the entire bus access. this pin is use for flash memory accesses and controls the we# input on the rom. 0 = write 1 = read pce[1]# 1o rst(m) peripheral chip enables specify which of the two memory address ranges are associated with current bus access. the pin remains valid during the entire bus access. pce[0]# 1o rst(m) peripheral chip enables specify which of the two memory address ranges are associated with current bus access. the pin remains valid during the entire bus access. total 31
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 19 table 6. primary pci bus signals (sheet 1 of 2) name count type description p_ad[31:0] 32 i/o sync(p) rst(p) primary pci address/data is the multiplexed pci address and lower 32 bits of the data bus. p_ad[63:32] 32 i/o sync(p) rst(p) primary pci address/data is the upper 32 bits of the pci data bus driven during the data phase. p_par 1i/o sync(p) rst(p) primary pci bus parity is even parity across p_ad[31:0] and p_c/be[3:0]# . p_par64 1i/o sync(p) rst(p) primary pci bus upper dword parity is even parity across p_ad[63:32] and p_c/be[7:4]# p_c/be[7:0]# 8i/o sync(p) rst(p) primary pci bus command and byte enables are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as byte enables for p_ad[63:0] . p_req# 1o sync(p) rst(p) primary pci bus request indicates to the pci bus arbiter that the i/o processor desires use of the pci bus. p_req64# 1i/o sync(p) rst(p) primary pci bus request 64-bit transfer indicates the attempt of a 64-bit transaction on the pci bus. when the target is 64-bit capable, the target acknowledges the attempt with the assertion of p_ack64# . p_idsel 1i sync(p) primary pci bus initialization device select is used to select the 80331 during a configuration read or write command on the pci bus. p_gnt# 1i sync(p) primary pci bus grant indicates that access to the pci bus has been granted. p_ack64# 1i/o sync(p) rst(p) primary pci bus acknowledge 64-bit transfer indicates that the device has positively decoded its a ddress as the target of the current access and the target is willing to transfer data using the full 64-bit data bus. p_frame# 1i/o sync(p) rst(p) primary pci bus cycle frame is asserted to indicate the beginning and duration of an access. p_irdy# 1i/o sync(p) rst(p) primary pci bus initiator ready indicates the initiating agent?s ability to complete the current data phase of the transaction. during a write, it indicates that valid data is present on the address/data bus. during a read, it indicates the processor is ready to accept the data. p_trdy# 1i/o sync(p) rst(p) primary pci bus target ready indicates the target agent?s ability to complete the current data phase of the transaction. during a read, it indicates that valid data is present on the address/data bus. during a write, it indicates the target is ready to accept the data. p_stop# 1i/o sync(p) rst(p) primary pci bus stop indicates a request to stop the current transaction on the pci bus. p_devsel# 1i/o sync(p) rst(p) primary pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. p_serr# 1i/o od sync(p) rst(p) primary pci bus system error is driven for address parity errors on the pci bus.
intel? 80331 i/o processor datasheet package information 20 august 2005 document number: 273943-004US p_perr# 1i/o sync(p) rst(p) primary pci bus parity error is asserted when a data parity error occurs during a pci bus transaction. p_m66en 1i/o primary pci bus 66 mhz enable indicates the speed of the pci bus. when this signal is sampled high the pci bus speed is 66 mhz, when low, the bus speed is 33 mhz. p_clk 1i primary pci bus input clock provides the timing for all pci transactions and is the clock source for most internal 80331 units. p_rst# 1i async reset brings pci-specific register s, sequencers, and signals to a consistent state. when p_rst# is asserted: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open drain signals such as p_serr# are floated. p_rst# may be asynchronous to p_clk when asserted or deasserted. although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. p_rcomp 1i/o pci resistor compensation pin is an analog pad that connects to the board resistor to control all pci output driver strengths (analog). total 90 note: when the pci bridge is disabled ( brg_en = 0), all primary pci interface signals become inactive, and the secondary interface becom es a primary pci interface. table 6. primary pci bus signals (sheet 2 of 2) name count type description
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 21 table 7. secondary pci bus signals (sheet 1 of 2) name count type description s_ad[31:0] 32 i/o sync(s) rst(s) secondary pci address/data is the multiplexed pci address and lower 32 bits of the data bus. s_ad[63:32] 32 i/o sync(s) rst(s) secondary pci address/data is the upper 32 bits of the pci data bus. s_par 1i/o sync(s) rst(s) secondary pci bus parity is even parity across s_ad[31:0] and s_c/be[3:0]# . s_par64 1i/o sync(s) rst(s) secondary pci bus upper dword parity is even parity across s_ad[63:32] and s_c/be[7:4]# . s_c/be[3:0]# 4i/o sync(s) rst(s) secondary pci bus command and byte enables are multiplexed on the same pci pins. during the address phase, they define the bus command. during the data phase, they are used as the byte enables for s_ad[31:0] . s_c/be[7:4]# 4i/o sync(s) rst(s) secondary pci byte enables are used as byte enables for s_ad[63:32] during secondary pci data phases. s_req64# 1i/o sync(s) rst(s) secondary pci bus request 64-bit transfer indicates the attempt of a 64-bit transaction on the secondary pci bus. when the target is 64-bit capable, the target acknowledges the attempt with the assertion of s_ack64# . s_ack64# 1i/o sync(s) rst(s) secondary pci bus acknowledge 64-bit transfer indicates the device has positively decoded its address as the target of the current access, indicates the target is willing to transfer data using 64 bits. s_frame# 1i/o sync(s) rst(s) secondary pci bus cycle frame is asserted to indicate the beginning and duration of an access. s_irdy# 1i/o sync(s) rst(s) secondary pci bus initiator ready indicates the initiating agent ability to complete current data phase of transaction. during a write, it indicates valid data is present on the secondary address/data bus. during a read, it indicates the processor is ready to accept the data. s_trdy# 1i/o sync(s) rst(s) secondary pci bus target ready indicates the target agent ability to complete the current data phase of the transaction. during a read, it indicates that valid data is present on the secondary address/data bus. during a write, it indicates the target is ready to accept the data. s_stop# 1i/o sync(s) rst(s) secondary pci bus stop indicates a request to stop the current transaction on the secondary pci bus. s_devsel# 1i/o sync(s) rst(s) secondary pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. s_serr# 1i/o od sync(s) rst(s) secondary pci bus system error is driven for address parity errors on the secondary pci bus. s_rst# 1o async secondary pci bus reset is an output based on p_rst# . it brings pci-specific registers, sequencers, and signals to a consistent state. when p_rst# is asserted, it causes s_rst# to assert and: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open drain signals such as s_serr# are floated. s_rst# may be asynchronous to s_clkin when asserted or deasserted. although asynchronous, deassertion must be ensured to be a clean, bounce-free edge.
intel? 80331 i/o processor datasheet package information 22 august 2005 document number: 273943-004US s_perr# 1i/o sync(s) rst(s) secondary pci bus parity error is asserted when a data parity error during a secondary pci bus transaction. s_clko[3:0] 4o secondary pci bus output clocks are used to drive external logic on the secondary pci bus. s_clkout 1o secondary pci bus output clock is used to drive s_clkin when the io processor provides secondary bus clocks. s_clkin/ p_clk 1 1i secondary pci bus input clock provides the timing for all pci transactions. typically connected on the board to s_clkout . provides the timing clock for all secondary pci interfaces. when the pci bridge is disabled ( brg_en =0), this is the primary pci input clock , driven by an external device. s_m66en 1i/o secondary pci bus 66 mhz enable indicates the speed of the secondary pci bus. when this signal is high, the bus speed is 66 mhz and when it is low, the bus speed is 33 mhz. s_req[3]#/ p_idsel 1 1i sync(s) secondary pci bus request is the request signal from device 3 on the secondary pci bus. when the pci bridge is disabled ( brg_en =0), this pin functions as pci bus initialization device select and is used to select the 80331 during a configuration read or write command on the pci bus. s_req[1]# p_gnt# 1 1i sync(s) secondary pci bus request is the request signal from device 1 on the secondary pci bus. when the pci bridge is disabled ( brg_en =0), this pin functions as primary pci bus grant indicating that access to the pci bus has been granted. s_req[2,0]# 2i sync(s) secondary pci bus requests are the request signals from devices 2 and 0 on the secondary pci bus. s_gnt[3,2]# 2o sync(a) rst(a) secondary pci bus grants are grant signals sent to devices 3 and 2 on the secondary pci bus. s_gnt[1]#/ p_req# 1 1o sync(s) rst(s) secondary pci bus grant is a grant signal sent to device 1 on the secondary pci bus. when the pci bridge is disabled ( brg_en =0), this pin functions as primary pci bus request and indicates to the pci bus arbiter that the i/o processor desires use of the pci bus. s_gnt[0]#/ p_bmi 1 1o/od sync(s) rst(s) secondary pci bus grant is a grant signal sent to device 0 on the secondary pci bus. when the pci bridge is disabled ( brg_en =0), this pin functions as pci bus master indicator to be used with external raidios logic for private device control. s_pcixcap 1i secondary pci-x capability is an analog pad that selects pci/x mode and frequency capabilities. non-standard, special purpose analog pin. s_rcomp 1i/o pci resistor compensation pin is an analog pad that connects to the board resistor to control all pci output driver strengths (analog). total 101 note: when the pci bridge is disabled ( brg_en =0), all secondary pci interface signals become primary interface signals. 1. these signal functions are only valid when brg_en=0 and arb_en=0. table 7. secondary pci bus signals (sheet 2 of 2) name count type description
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 23 table 8. interrupt signals name count type description p_int[d:a]# 4o od async rst(p) primary pci bus interrupt requests an interrupt. the assertion and deassertion of p_int[d:a]# is asynchronous to p_clk . a device asserts its p_int[d:a]# line when requesting attention from its device driver. once the p_int[d:a]# signal is asserted, it remains asserted until the device driver clears the pending request. p_int[d:a]# interrupts are level sensitive. s_int[d:a]# 4i async rst(s) secondary pci bus interrupt requests an interrupt. the assertion and deassertion of s_int[d:a]# is asynchronous to s_clkin . a device asserts its s_int[d:a]# line when requesting attention from its device driver. once the s_int[d:a]# signal is asserted, it remains asserted until the device driver clears the pending request. s_int[d:a]# interrupts are level sensitive. hpi# 1i async high priority interrupt causes a high priority interrupt to the i/o processor. this pin is leve l-detect only and is internally synchronized. total 9 table 9. i 2 c signals name count type description scl0 1 i/o i 2 c clock provides synchronous operation of the i 2 c bus zero. scd0 1 i/o i 2 c data is used for data transfer and arbitration of the i 2 c bus zero. scl1 1 i/o i 2 c clock provides synchronous operation of the i 2 c bus one. scd1 1 i/o i 2 c data is used for data transfer and arbitration of the i 2 c bus one. to ta l 4
intel? 80331 i/o processor datasheet package information 24 august 2005 document number: 273943-004US table 10. uart signals (sheet 1 of 2) name count type description gpio[0]/ u0_rxd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. serial input : serial data input from device pin to receive shift register. gpio[1]/ u0_txd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. serial output : composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. gpio[2]/ u0_cts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. clear to send : when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart should stop transmission to prevent overflow of the receiving uarts buffer. the cts# signal is a modem-status input whose condition may be tested by the host processor or by the uart when in autoflow mode as described below: non-autoflow mode : when not in autoflow mode, bit 4 (cts) of the modem status register (msr) indicates the state of cts# . bit 4 is the complement of the cts# signal. bit 0 (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user may program the uart to interrupt the processor when dcts changes state. the programmer may then stall the outgoing data stream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user may not receive an msr interrupt when cts# reasserts. this occurs because disabling the uart also disables interrupts. as a workaround, the user may use auto cts in autoflow mode, or program the cts# pin to interrupt. autoflow mode : note: in autoflow mode, the uart transmit circuitry will check the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. gpio[3]/ u0_rts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpos e inputs or outputs. the default mode is a general purpose input. request to send : when low, this informs the remote device that the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. non-autoflow mode : the rts# output signal may be asserted by setting bit 1 (rts) of the modem control register to a 1. the rts bit is the complement of the rts# signal. autoflow mode : rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programmed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold.
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 25 gpio[4]/ u1_rxd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. serial input : serial data input from device pin to receive shift register. gpio[5]/ u1_txd 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. serial output : composite serial data output to the communications link-peripheral, modem, or data set. the txd signal is set to the marking (logic 1) state upon a reset operation. gpio[6]/ u1_cts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. clear to send : when low, this pin indicates that the receiving uart is ready to receive data. when the receiving uart deasserts cts# high, the transmitting uart should stop transmission to prevent overflow of the receiving uarts buffer. the cts# signal is a modem-status input whose condition may be tested by the host processor or by the uart when in autoflow mode as described below: non-autoflow mode : when not in autoflow mode, bit 4 (cts) of the modem status register (msr) indicates the state of cts# . bit 4 is the complement of the cts# signal. bit 0 (dcts) of the modem status register indicates whether the cts# input has changed state since the previous reading of the modem status register. cts# has no effect on the transmitter. the user may program the uart to interrupt the processor when dcts changes state. the programmer may then stall the outgoing data stream by starving the transmit fifo or disabling the uart with the ier register. note: when uart transmission is stalled by disabling the uart, the user may not receive an msr interrupt when cts# reasserts. this occurs because disabling the uart also disables interrupts. as a workaround, the user may use auto cts in autoflow mode, or program the cts# pin to interrupt. autoflow mode : note: in autoflow mode, the uart transmit circuitry will check the state of cts# before transmitting each byte. when cts# is high, no data is transmitted. gpio[7]/ u1_rts# 1i/o general purpose i/o : these pins may be selected on a per pin basis as general purpose inputs or outputs. the default mode is a general purpose input. request to send : when low, this informs the remote device that the uart is ready to receive data. a reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. non-autoflow mode : the rts# output signal may be asserted by setting bit 1 (rts) of the modem control register to a 1. the rts bit is the complement of the rts# signal. autoflow mode : rts# is automatically asserted by the autoflow circuitry when the receive buffer exceeds its programm ed threshold. it is deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. total 8 table 10. uart signals (sheet 2 of 2) name count type description
intel? 80331 i/o processor datasheet package information 26 august 2005 document number: 273943-004US table 11. test and miscellaneous signals name count type description tck 1i test clock provides clock input for ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the device on the rising clock edge and data is clocked out on the falling clock edge. tdi 1i sync(t) test data input is the jtag serial input pin. tdi is sampled on the rising edge of tck , during the shift-ir and shift-dr states of the test access port. this signal has a weak internal pull-up to ensure proper operation when this pin is not being driven. tdo 1o sync(t) rst(t) test data output is the serial output pin for the jtag feature. tdo is driven on the falling edge of tck during the shift-ir and shift-dr states of the test access port. at other times, tdo floats. the behavior of tdo is independent of p_rst# . trst# 1i async test reset asynchronously resets the test access port controller function of ieee 1149 boundary scan testing (jtag). this pin has a weak internal pull-up. tms 1i sync(t) test mode select is sampled on the rising edge of tck to select the operation of the test logic for ieee 1149 boundary scan testing. this pin has a weak internal pull-up. n/c 64 - no connect . do not connect to any signal, power or ground. pu1 1i pullup 1 must be pulled high. note: this signal was formerly known as p_lock# . pu2 1i pullup 2 must be pulled high. is controlled by pciodt_en . note: this signal was formerly known as s_lock# . pwrdelay 1i async power fail delay is used to delay the reset of the memory controller in a power-fail condition. this allows the self-refresh command to be sent to the ddr sdram array. total 72
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 27 table 12. reset strap signals (sheet 1 of 2) name count type description retry 1c configuration retry mode : retry is latched on the rising (deasserting) edge of p_rst# and determines when the pci interface of the atu will disable pci configuration cycles by signaling a retry until the configuration cycle retry bit is cleared in the pci configuration and status register. 0 = configuration cycles enabled (requires pull down resistor.) 1 = configuration retry enabled in the atu (default mode) note: muxed onto signal ad[6] , see table 15, ?pin multiplexing for functional modes? on page 33 . core_rst# 1c core reset mode is latched on the rising (deasserting) edge of p_rst# and determines when the intel xscale ? core is held in reset until the processor reset bit is cleared in pci configuration and status register. 0 = hold in reset. (requires pull-down resistor.) 1 = do not hold in reset. (default mode) note: muxed onto signal ad[5] , see table 15, ?pin multiplexing for functional modes? on page 33 . p_boot16# 1c bus width is latched on the rising (deasserting) edge of p_rst# , it sets the default bus width for the pbi memory boot window. 0 = 16 bits wide (requires a pull-down resistor.) 1 = 8 bits wide (default mode) note: muxed onto signal ad[4] , see table 15, ?pin multiplexing for functional modes? on page 33 . mem_type 1c memory type : mem_type is latched on the rising (deasserting) edge of p_rst# and it defines the speed of the ddr sdram interface. 0 = ddr-ii sdram at 400 mhz (required pull-down resistor.) 1 = ddr sdram at 333 mhz (default mode) note: muxed onto signal ad[2] , see table 15, ?pin multiplexing for functional modes? on page 33 . s_pcix133en 1 config secondary pci bus 133 mhz enable : s_pcix133en latched on rising (deasserting) edge of p_rst# and determines maximum pci-x mode operating frequency. 0 = 100 mhz enabled (requires pull down resistor.) 1 = 133 mhz enabled (default mode) note: muxed onto signal ad[3] , see table 15, ?pin multiplexing for functional modes? on page 33 . privmem 1 config private memory enable: privmem latched at rising (deasserting) edge of p_rst# and determines if 80331 operates with private memory space on the secondary pci bus of the pci-to-pci bridge. 0 = normal addressing mode (requires pull-down resistor) 1 = private addressing enable in pci-to-pci bridge. (default mode). note: muxed onto signal a[1] , see table 15, ?pin multiplexing for functional modes? on page 33 . privdev 1 config private device enable: privdev latched at rising (deasserting) edge of p_rst# and determines if 80331 operates with private device enabled on the secondary pci bus of the pci-to-pci bridge. 0 = all secondary pci devices are accessible to primary pci config cycles. (requires pull-down resistor) 1 = private devices enabled in pci-to-pci bridge. (default mode) note: muxed onto signal a[0] , see table 15, ?pin multiplexing for functional modes? on page 33 .
intel? 80331 i/o processor datasheet package information 28 august 2005 document number: 273943-004US brg_en 1config bridge enable : brg_en latched at rising (deasserting) edge of p_rst# and determines if 80331 operates with pci-to-pci bridge. 0 = disable bridge, enable p_clk input on s_clkin input. (requires pull-down resistor) 1 = enabled bridge. (default mode) note: muxed onto signal ad[0] , see table 15, ?pin multiplexing for functional modes? on page 33 . arb_en 1config internal arbiter enable: arb_en is latched on the rising (deasserting) edge of p_rst# and it determines if the pci interface will enable the integrated arbiter, or use an external arbiter. note : arb_en only valid when pci bridge disabled ( brg_en =0). 0 = internal arbiter disabled (requires pull-down resistor). 1 = internal arbiter enabled (default mode). note: muxed onto signal ad[1] , see table 15, ?pin multiplexing for functional modes? on page 33 . p_32bitpci# 1config primary pci-x bus width : p_32bitpci# is latched on the rising (deasserting) edge of p_rst#, and by default, identifies 80331 subsystem as 64-bit unless the appropriate pull-down resistor is used. this strap sets bit 16 in the pci-x bridge status register. 0 = 32 bit wide bus. (requires pull-down resistor). 1 = 64 bit wide bus. (default mode). note: muxed onto signal a[2] , see table 15, ?pin multiplexing for functional modes? on page 33 . pciodt_en 1c pci bus odt enable : pciodt_en is latched on the rising (deasserting) edge of p_rst#, and determines when the pci-x interface will have on die termination enabled. pci odt enable is valid for the secondary pci bus only. the following signals are affected by pciodt_en: s_ad[63:32], s_c/be[7:4]#, s_par64, s_req64#, s_req[3:0]#, s_ack64#, s_frame#, s_irdy#, s_devsel#, s_trdy#, s_stop#, s_perr#, s_lock#, s_m66en, s_serr#, s_int[d:a]# 0 = odt disabled on the secondary pci bus. (requires pull-down resistor). 1 = odt enabled on the secondary pci bus. (default mode). note: muxed onto signal a[20] , see table 15, ?pin multiplexing for functional modes? on page 33 . total 11 table 12. reset strap signals (sheet 2 of 2) name count type description
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 29 table 13. power and ground pins name count type description v ccpll[1-5] 4pwr pll 1-5 power is a separate v cc15 supply ball for the phase lock loop clock generator. it is to be connected to the board v cc15 plane. each v ccpll requires a lowpass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. see the intel ? 80331 i/o processor design guide for more information. note: there is no vccpll3 signal. v cc33 49 pwr 3.3 v power balls to be connected to a 3.3 v power board plane. v cc25/18 29 pwr 2.5 v/1.8 v power balls to be connected to a 2.5 v or 1.8 v power board plane, dependent on ddr or ddrii mode. v cc15 58 pwr 1.5 v power balls to be connected to a 1.5 v power board plane. v cc13 7pwr 1.3 v power balls to be connected to a 1.35 v power board plane. ddr_vref 1i sdram voltage reference is used to supply the reference voltage to the differential inputs of the memory controller pins. v ss 226 gnd ground balls to be connected to a ground board plane. v ssa[1-5] 4gnd analog ground balls need to be connected to the appropriate v ccpll filter, and not to board ground. note: there is no vssa3 signal.
intel? 80331 i/o processor datasheet package information 30 august 2005 document number: 273943-004US table 14. pin mode behavior (sheet 1 of 3) pin reset lind reset lind nobrg norm lind norm lind nobrg ecc off ddr 32bit ddr 32bit p_pci 32bit s_pci m_ck[2:0] x (1) x (1) vo vo vo vo - - m_ck[2:0]# x (1) x (1) vo vo vo vo - - m_rst# 0 0 vo vo vo vo - - ma[13:0] 0* 0* vo vo vo vo - - ba[1:0] 0* 0* vo vo vo vo - - ras# 1* 1* vo vo vo vo - - cas# 1* 1* vo vo vo vo - - we# 1* 1* vo vo vo vo - - cs[1:0]# 1* 1* vo vo vo vo - - cke[1:0] 0* 0* vo vo vo vo - - dq[63:32] z* z* vb vb vb id,z - - dq[31:0] z* z* vb vb vb vb - - cb[7:0] z* z* vb vb vb vb - - dqs[8] z* z* vb vb id,z vb - - dqs[7:4] z* z* vb vb vb id,z - - dqs[3:0] z* z* vb vb vb vb - - dqs[8]# z* z* vb vb id,z vb - - dqs[7:4]# z* z* vb vb vb id,z - - dqs[3:0]# z* z* vb vb vb vb - - dm[8] z* z* vo vo z vo - - dm[7:4] z* z* vo vo vo z - - dm[3:0] z* z* vo vo vo vo - - ddr_vref vi vi vi vi vi vi - - odt[1:0] (2) 0 0 vo vo vo vo - - ddrres[2:1] z* z* vb vb vb vb - - ddrcres0 0 0 0000 - - ddrslwcres vb vb vb vb vb vb - - ddrimpcres vb vb vb vb vb vb - - a[22:16] h h vo vo - - - - ad[15:0] hhvbvb-- - - a[2:0] h h vo vo - - - - ale 0 0 vo vo - - - - poe# 1 1 vo vo - - - - pwe# 1 1 vo vo - - - - pce[1]# h h vo vo - - - - pce[0]# h h vo vo - - - - p_ad[63:32] zzvbh--h - p_ad[31:0] 0zvbh--vb- p_par zzvbh--vb-
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 31 p_par64 zzvbh--h - p_c/be[7:4]# zzvbh--h - p_c/be[3:0]# zzvbh--vb- p_req# 1zvoz-- - - p_req64# vi h vb h - - - - p_idsel vi h vi h - - - - p_gnt# vi h vi h - - - - p_ack64# zhvbh-- - - p_frame# zhvbh-- - - p_irdy# zhvbh-- - - p_trdy# vi h vb h - - - - p_stop# vi h vb h - - - - p_devsel# vi h vb h - - - - p_lock# zhvbh-- - - p_serr# zhvbh-- - - p_clk vi h vi h - - - - p_rst# vi vi vi vi - - - - p_perr# zhvbh-- - - p_m66en vb h vb h - - - - s_ad[63:32] zzvbvb---h s_ad[31:0] 0zvbvb-- - - s_par 0zvbvb-- - - s_par64 zzvbvb---h s_c/be[3:0]# 0zvbvb-- - - s_c/be[7:4]# zzvbvb---h s_req64# vo vi vb vb - - - - s_ack64# zzvbvb-- - - s_frame# zzvbvb-- - - s_irdy# zzvbvb-- - - s_trdy# vo vi vb vb - - - - s_stop# vo vi vb vb - - - - s_devsel# vo vi vb vb - - - - s_serr# zzvbvb-- - - s_rst# vo z vo z - - - - s_perr# zzvbvb-- - - s_lock# zzvbvb-- - - s_clko[3:0] vo z vo z - - - - s_clkout vo z vo z - - - - table 14. pin mode behavior (sheet 2 of 3) pin reset lind reset lind nobrg norm lind norm lind nobrg ecc off ddr 32bit ddr 32bit p_pci 32bit s_pci
intel? 80331 i/o processor datasheet package information 32 august 2005 document number: 273943-004US s_clkin vi vi vi vi - - - - s_m66en vb vb vb vb - - - - s_req[3]#/ p_idsel vi vi vi vi - - - - s_req[1]#/ p_gnt# vi vi vi h - - - - s_req[2,0]# vi h vi h - - - - s_gnt[3,2]#, hhvoh-- - - s_gnt[1]#/ p_req# h h vo vo - - - - s_gnt[0]#/ p_bmi h h vo vo - - - - s_pcixcap vi vss vi vss - - - - p_rcomp ao ao ao ao - - - - s_rcomp ao ao ao ao - - - - p_int[d:a]# zz (3) z/0 z (3) -- - - s_int[d:a]# vi id vi id - - - - hpi# vi vi vi vi - - - - scl0, scd0, scl1, scd1 hhvbvb-- - - gpio[3:0]/ u0_rts#, u0_cts#, u0_txd, u0_rxd, vi vi vb vb - - - - gpio[7:4]/ u1_rts#, u1_cts#, u1_txd, u1_rxd vi vi vb vb - - - - tck vi vi vi vi - - - - tdi hhhh-- - - tdo (4) vo* vo* vo vo - - - - trst# hhhh-- - - tms hhhh-- - - pwrdelay vi vi vi vi - - - - nc[3:0] hhhh-- - - notes: 1 = driven to v cc 0 = driven to v ss x = driven to unknown state id = the input is disabled. h = pulled up to v cc pd = pull-up disabled l = pulled down to v ss z = output disabled (floats) vb = acts like a valid bidirectional pin. vo = a valid output level is driven. vi = need to drive a valid input level. * = after power fail sequence completes. ** = caused by hi-z from mode pins only. ao = analog output level. 1. clocks become valid right before m_rst# deasserts. 2. odt signal to be low during power up and initialization per ddrii jedec specification. 3. p_int[a]# is the only active ouput in 80331 no bridge mode. 4. test inputs pulled up as noted in signal description table table 11, ?test and miscellaneous signals? on page 26 and test outputs tristated during normal functional operation. table 14. pin mode behavior (sheet 3 of 3) pin reset lind reset lind nobrg norm lind norm lind nobrg ecc off ddr 32bit ddr 32bit p_pci 32bit s_pci
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 33 table 15. pin multiplexing for functional modes pin bridge disabled reset straps a[20] - pciodt_en ad[6] - retry ad[5] - core_rst# ad[4] - p_boot16# ad[3] - s_pcix133en ad[2] - mem_type ad[1] - arb_en ad[0] - brg_en a[2] - p_32bitpci# a[1] - privmem a[0] - privdev s_req[3]# p_idsel - s_req[1]# p_gnt# - s_gnt[1]# p_req# - s_gnt[0]# p_bmi - s_clkin p_clk -
intel? 80331 i/o processor datasheet package information 34 august 2005 document number: 273943-004US figure 2. 829-ball fcbga package diagram table 16. fc-style, h-pbga package dimensions 829-pin bga symbol minimum maximum a 2.392 2.942 a1 0.50 0.70 a3 0.742 0.872 b 0.61 ref. c 1.15 1.37 d 37.45 37.55 e 37.45 37.55 f1 9.88 ref. f2 10.16 ref. e 1.27 ref. s1 0.97 ref. s2 0.97 ref. note: measurement in millimeters. b1230-02 e d f1 f2 die laser mark s2 s1 pin #1 corner ?b e a3 a a1 c top view bottom view side view seating plane a 1234 b c d e f g h j k l n p r t u v w y aa ab ac ad ae af ag ah aj m 5 6 7 8 9 10111213141516171819 202122232425 26272829
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 35 figure 3. intel ? 80331 i/o processor ballout (bottom view) b1210-0 1 ddrii/sdram jtag gpio pbi vcc/vss primary pci-x bus secondary pci-x bus aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10111213 14 151617181920 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10111213 14 151617181920 21 22 23 24 25 26 27 28 29
intel? 80331 i/o processor datasheet package information 36 august 2005 document number: 273943-004US figure 4. intel ? 80331 i/o processor ballout - left side (bottom view) b3969-01 af 12345 6 78910111213 12345 678910111213 ae ad 14 15 14 15 aj ah ag ac ab aa y w v u t r p n m l k j h g f e d c b a vss vss vss cke0 dm1 vss dq9 dq13 dq8 dq21 dq29 dq30 cb1 vss vss vss vss vss vss vss tdo tms vss vss vss vcc15 vss tck vss vss vcc13 vcc13 vcc15 vss n/c n/c vss n/c n/c n/c vss vss n/c n/c n/c n/c vss vss vss vss vss vss tdi n/c n/c n/c n/c vss vss hpi# vss vss vss vss vss vcc13 vcc13 vcc13 vcc15 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vss vss vss vss vss vss vss vss vss vss vss nb nb nb dqs1# dqs1 dq15 dq10 dq17 dq28 dq25 dq24 dq20 dq14 dq16 dqs3 dq31 dq18 ma4 ma3 ma1 ma7 ma11 ma9 ma2 cb5 cb4 ma0 ba1 dq11 dm2 dm3 ma8 m_ck1 m_ ck1# nb nb nb vss vss vss dq6 dq2 ma12 dq5 n/c n/c dm0 dqs0# dqs0 ddr_ vref p_ c/be4# p_ c/be5# p_ c/be7# p_ c/be6# n/c n/c n/c n/c trst# p_ ad63 p_ ad45 p_ ad60 p_ ad61 p_ ad62 p_ ad59 p_ ad56 p_ ad53 p_ ad50 p_ ad49 p_ ad0 p_ ad3 p_ ad6 p_ c/be0# p_ ad10 p_ ad13 p_ ad58 p_ ad57 p_ ad41 p_ idsel p_ ad48 p_ ad32 p_ req64# p_ req# n/c p_gnt# n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c p_ devsel# p_ stop# p_ trdy# p_ perr# p_ ad4 p_ m66en p_ ad7 p_ ad8 p_ ad9 p_ ad11 p_ ad12 p_ ad17 p_ ad22 p_ ad28 p_ ad31 p_ ad25 p_ ad30 p_ ad14 p_ ad15 p_ ad16 p_ ad18 p_ ad21 p_ ad26 p_ ad29 p_ ad20 p_ ad23 p_ c/be1# p_ c/be3# p_ par p_ ad19 p_ ad24 p_ ad27 p_ c/be2# p_ frame# p_ irdy# p_ ad5 p_ clk p_ ad1 p_ ad2 p_ ack64# p_ serr# p_ ad52 p_ ad51 p_ ad55 p_ ad46 p_ ad44 p_ ad40 p_ ad43 p_ ad42 p_ ad47 p_ par64 pwr delay p_ inta# p_ rst# p_ rcomp p_ intb# p_ intc# p_ intd# dq4 dq1 dq0 dq7 dqs2 dqs2# dq23 dq26 dq27 dq19 dq22 dq12 cb0 vss vss vss vss vss vcc33 vcc33 vcc15 vcc15 vcc13 vcc33 vcc15 vcc15 vcc13 vss vss vss vss vss vcc15 vcc15 vss vcc15 vcc33 vcc33 vss vcc15 vss vcc15 vcc15 vss vss vss vss p_ ad39 vss vcc15 vcc pll4 vcc pll5 vssa5 vss vss vcc15 vcc15 vcc33 p_ ad54 p_ ad38 vcc33 vcc33 vss vss vss n/c n/c n/c vcc15 vcc15 vcc33 vcc33 n/c n/c n/c n/c n/c p_ ad37 p_ ad36 vcc15 vss vcc15 vss vcc15 vss vss vcc15 vss vss vss vss vcc15 vcc15 vcc15 vcc33 vss vcc33 n/c n/c vss n/c vss vss vcc33 vss vss vss vss vss vcc33 vcc33 vcc33 vcc33 vss vss vss vss vss vss vss vss vss vss vcc15 vcc15 vcc15 vss vcc15 vss vss vss vss vss vss n/c vss pu1 vss vss vss vss vcc33 vss vss vss vcc15 vcc15 vss vcc15 vss vcc15 vss vss vss vcc15 vcc15 vcc15 vss vss vcc pll2 vssa2 vcc15 vss vss vcc15 vss vss vss vss vss vss dqs3# m_rst# cke1 dq3 dm8 ma5 ma6 p_ ad35 p_ ad34 p_ ad33
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 37 figure 5. intel ? 80331 i/o processor ballout - right side (bottom view) b3970-01 16 17 18 19 20 21 22 23 24 25 26 27 28 29 16 17 18 19 20 21 22 23 24 25 26 27 28 29 af ae ad aj ah ag ac ab aa y w v u t r p n m l k j h g f e d c b a m_ck0 odt0 scl1 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 s_ rcomp s_ clko0 s_ req64# s_ c/be7# dq35 dq40 dqs8 dq36 dq38 dq39 dq34 dq37 dq32 dq33 dq53 dq62 dq49 dm6 dq43 dq42 dqs5 dq54 dq50 dq57 dq63 dqs5# dqs6 dqs6# ba0 ma10 cb6 cb2 cb7 m_ck2# m_ck2 m_ck0# cb3 dqs8# dqs4 dqs4# dm4 vss nb nb vss nb nb nb nb vss vss vss vss vss vss vss vss vss vss vss vss cs1# vss vss vss vss vss dq55 dm5 dm7 ma13 vss odt1 cs0# we# vss ddr res1 gpio2/ u0_cts# gpio3/ u0_rts# gpio6/ u1_cts# gpio7/ u1_rts# gpio5/ u1_txd gpio4/ u1_rxd gpio0/ u0_rxd gpio1/ u0_txd vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 vcc 25/18 ddr cres0 a16 ad0 ddrslw cres ddrimp cres a20 ddr res2 a1 vss vss vcc15 vss vss vss vcc15 ras# scd1 vcc15 vss vss vss vss ale a21 ad1 vcc15 vss vss vcc15 vcc15 vss vss ad10 ad4 ad3 ad13 ad8 ad5 s_ ad52 s_ ad51 s_ ad57 s_ ad61 a0 scl0 ad7 ad6 s_rst# s_ gnt2# s_ gnt3# a18 ad14 ad12 a2 a22 a19 poe# pwe# ad15 ad11 ad2 a17 ad9 scd0 cas# s_ pcixcap s_ intd# s_ ad50 s_ ad49 s_ intc# s_ ad48 s_ inta# s_ intb# vss vcc15 vcc15 vss vss vss vss vcc33 pce1# pce0# vcc33 vcc33 vcc33 vcc33 vss vssa4 vcc15 vss vcc33 vcc33 vss vcc15 vss vss vss vcc15 vcc33 vcc33 vcc33 vcc15 vss vss vcc33 vcc33 vcc33 vss vss vss vcc15 vss vss vcc33 vss vss vcc33 vcc33 vcc33 vss vss vss vcc15 vss vssa1 vss vss vcc15 vss vss s_ c/be1# s_ c/be2# s_ c/be3# s_ c/be6# s_ c/be5# s_ ack64# s_ c/be0# s_ ad14 s_ ad15 s_ ad9 s_ ad10 s_ ad13 s_ ad12 s_ ad30 s_ ad31 s_ ad25 s_ ad26 s_ ad1 s_ ad46 s_ clko3 s_ ad2 s_ ad37 s_ ad32 s_ ad39 s_ gnt0# s_ ad17 s_ ad18 s_ ad19 s_ ad6 s_ ad35 s_ ad38 s_ ad41 s_ ad42 s_ ad47 s_ ad3 s_ ad4 s_ ad5 s_ ad27 s_ ad28 s_ ad29 s_ ad7 s_ ad8 s_ ad11 vcc15 vss vss vss vss vss vss pu2 vss vcc33 vcc33 vcc33 vss s_ serr# vss vss vss vss vss vss vss vss vss vcc15 vss vss vss vss vcc33 vcc33 vcc33 vss vcc33 vcc33 s_par vcc33 vcc33 vss s_ clko1 s_ clko2 s_ clkout s_ perr# s_ devsel# vss s_ clkin vss vss vss vss vss vcc15 vcc pll1 s_ ad53 s_ ad33 vss s_ ad55 s_ ad54 s_ ad34 vcc33 s_ ad60 s_ ad36 s_ ad62 s_ ad0 s_ irdy# s_ req2# s_ ad24 s_ ad22 s_ ad16 s_ ad21 s_ frame# s_ stop# s_ trdy# s_ req1# s_ ad23 s_ m66en s_ ad20 s_ ad45 s_ ad44 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c s_ gnt1# vss s_ req3# s_ req0# s_ c/be4# s_ par64 s_ ad43 s_ ad40 s_ ad63 s_ ad59 s_ ad58 s_ ad56 vcc33 n/c vcc33 vss vcc15 vss vss vss vss vcc15 vcc33 dq45 dq61 dq41 dq46 dq47 dq48 dq52 dq51 dq56 dq59 dq58 dqs7 dqs7# dq60 dq44
intel? 80331 i/o processor datasheet package information 38 august 2005 document number: 273943-004US table 17. 829-lead package - alphabetical ball listings (sheet 1 of 7) ball signal ball signal ball signal a1 -- b13 vss c25 s_ad21 a2 -- b14 vss c26 s_ad17 a3 vss b15 vss c27 s_c/be2# a4 p_ad16 b16 vss c28 s_frame# a5 p_ad18 b17 n/c c29 vcc33 a6 p_ad21 b18 n/c d1 p_ad10 a7 p_c/be3# b19 vss d2 p_ad11 a8 p_ad26 b20 vss d3 p_ad12 a9 p_ad29 b21 s_ad30 d4 vcc33 a10 vss b22 vss d5 p_c/be2# a11 n/c b23 s_ad26 d6 p_ad19 a12 n/c b24 s_gnt1# d7 vss a13 vcc15 b25 vss d8 p_ad24 a14 vss b26 s_ad18 d9 p_ad27 a15 vcc15 b27 s_ad16 d10 vss a16 vss b28 vss d11 n/c a17 vss b29 -- d12 n/c a18 n/c c1 vcc33 d13 vss a19 n/c c2 p_ad13 d14 n/c a20 n/c c3 p_ad14 d15 n/c a21 s_ad31 c4 p_par d16 n/c a22 s_ad29 c5 p_ad17 d17 vss a23 s_gnt0# c6 vcc33 d18 n/c a24 s_ad24 c7 p_ad22 d19 n/c a25 s_ad22 c8 p_ad25 d20 vss a26 s_ad19 c9 vcc33 d21 s_ad8 a27 vss c10 p_ad30 d22 s_ad27 a28 -- c11 n/c d23 vss a29 -- c12 n/c d24 s_ad23 b1 -- c13 vcc15 d25 s_ad20 b2 vss c14 n/c d26 vcc33 b3 p_ad15 c15 vss d27 s_c/be3# b4 p_c/be1# c16 n/c d28 s_stop# b5 vss c17 n/c d29 vss b6 p_ad20 c18 vcc15 e1 p_c/be0# b7 p_ad23 c19 n/c e2 vss b8 vss c20 s_m66en e3 p_m66en b9 p_ad28 c21 vcc33 e4 p_ad9 b10 p_ad31 c22 s_ad28 e5 vss b11 vss c23 s_ad25 e6 p_frame# b12 n/c c24 vcc33 e7 n/c
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 39 e8 vss f20 s_ad9 h3 p_ad1 e9 vcc33 f21 vcc33 h4 p_ad2 e10 vss f22 s_ad5 h5 vcc33 e11 vss f23 s_ad1 h6 p_ack64# e12 n/c f24 vss h7 n/c e13 n/c f25 s_clko2 h8 n/c e14 vcc15 f26 s_par h9 n/c e15 n/c f27 vss h10 p_trdy# e16 vcc15 f28 s_req1# h11 p_req# e17 n/c f29 s_devsel# h12 n/c e18 n/c g1 p_ad3 h13 n/c e19 vss g2 p_ad4 h14 vss e20 s_ad10 g3 p_ad5 h15 vcc15 e21 s_req2# g4 vss h16 vss e22 vss g5 p_devsel# h17 s_c/be1# e23 s_ad2 g6 p_stop# h18 s_ad14 e24 s_ad0 g7 vss h19 s_ad11 e25 vss g8 vss h20 s_c/be0# e26 s_serr# g9 p_clk h21 s_ad6 e27 pu2 g10 vcc33 h22 s_ad3 e28 s_trdy# g11 p_req64# h23 s_clko3 e29 s_irdy# g12 p_gnt# h24 s_clko0 f1 p_ad6 g13 vss h25 vss f2 p_ad7 g14 n/c h26 vcc33 f3 vcc33 g15 vss h27 vss f4 p_ad8 g16 n/c h28 vss f5 p_irdy# g17 vss h29 vss f6 vcc33 g18 s_ad15 j1 p_ad49 f7 n/c g19 s_ad12 j2 p_ad48 f8 vss g20 vss j3 vcc33 f9 vss g21 s_ad7 j4 p_perr# f10 vss g22 s_ad4 j5 p_serr# f11 n/c g23 vcc33 j6 vss f12 vss g24 s_clko1 j7 pu1 f13 n/c g25 s_clkout j8 n/c f14 n/c g26 vss j9 vss f15 vss g27 s_clkin j10 vcc15 f16 n/c g28 vss j11 vss f17 n/c g29 s_perr# j12 vcc15 f18 vss h1 p_ad0 j13 vss f19 s_ad13 h2 vss j14 vcc15 table 17. 829-lead package - alphabetical ball listings (sheet 2 of 7) ball signal ball signal ball signal
intel? 80331 i/o processor datasheet package information 40 august 2005 document number: 273943-004US j15 vss k27 s_c/be4# m10 vss j16 vcc15 k28 s_c/be5# m11 vccpll2 j17 vss k29 s_par64 m12 vssa2 j18 vcc33 l1 p_ad53 m13 vcc15 j19 vss l2 vss m14 vss j20 vcc33 l3 p_ad52 m15 vcc15 j21 vss l4 p_ad51 m16 vss j22 s_ad47 l5 vcc33 m17 vcc15 j23 s_ad46 l6 p_ad35 m18 vssa1 j24 vcc33 l7 p_ad34 m19 vccpll1 j25 s_ad45 l8 p_ad33 m20 vss j26 s_ad44 l9 vss m21 vcc33 j27 vcc33 l10 vcc15 m22 s_ad38 j28 s_ack64# l11 vss m23 s_ad37 j29 s_req64# l12 vcc15 m24 vss k1 p_ad50 l13 vss m25 s_ad36 k2 n/c l14 vss m26 s_ad62 k3 p_idsel l15 vss m27 vcc33 k4 vss l16 vss m28 s_ad61 k5 n/c l17 vss m29 s_ad60 k6 n/c l18 vcc15 n1 p_ad59 k7 vss l19 vss n2 p_ad58 k8 p_ad32 l20 vcc33 n3 p_ad57 k9 vcc15 l21 vss n4 vss k10 vcc15 l22 s_ad41 n5 p_ad41 k11 vcc15 l23 s_ad39 n6 p_ad40 k12 vss l24 s_ad40 n7 vss k13 vcc15 l25 vcc33 n8 p_ad39 k14 vss l26 s_c/be6# n9 vss k15 vss l27 s_c/be7# n10 vcc15 k16 vss l28 vss n11 vss k17 vcc33 l29 s_ad63 n12 vcc15 k18 vss m1 p_ad56 n13 vss k19 vcc33 m2 p_ad55 n14 vcc15 k20 vss m3 vcc33 n15 vss k21 vcc33 m4 p_ad54 n16 vcc15 k22 s_ad42 m5 p_ad38 n17 vss k23 vss m6 vcc33 n18 vcc15 k24 s_ad43 m7 p_ad37 n19 vss k25 s_req3# m8 p_ad36 n20 vcc33 k26 vss m9 vcc15 n21 vss table 17. 829-lead package - alphabetical ball listings (sheet 3 of 7) ball signal ball signal ball signal
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 41 n22 s_ad35 r5 p_ad45 t17 vcc15 n23 vcc33 r6 vcc33 t18 vss n24 s_ad34 r7 p_ad46 t19 vcc15 n25 s_req0# r8 p_ad47 t20 vss n26 vcc33 r9 vss t21 ad10 n27 s_ad59 r10 vcc15 t22 ad6 n28 s_ad57 r11 vss t23 ad4 n29 s_ad58 r12 vcc15 t24 s_intc# p1 p_ad60 r13 vss t25 vss p2 vss r14 vcc15 t26 s_ad49 p3 p_ad61 r15 vccpll4 t27 s_ad50 p4 p_ad62 r16 vssa4 t28 vss p5 vss r17 vss t29 s_rcomp p6 p_ad44 r18 vcc15 u1 p_c/be4# p7 p_ad43 r19 vss u2 p_c/be5# p8 p_ad42 r20 vcc33 u3 p_c/be7# p9 vcc15 r21 s_pcixcap u4 vss p10 vss r22 s_rst# u5 n/c p11 vcc15 r23 s_intd# u6 n/c p12 vss r24 vcc33 u7 vcc33 p13 vccpll5 r25 n/c u8 n/c p14 vssa5 r26 s_ad51 u9 vss p15 vcc15 r27 vcc33 u10 vcc15 p16 vss r28 s_ad52 u11 vss p17 vcc15 r29 s_ad53 u12 vcc13 p18 vss t1 n/c u13 vss p19 vcc15 t2 vss u14 vcc15 p20 vss t3 p_c/be6# u15 vss p21 vcc33 t4 n/c u16 vcc15 p22 s_gnt2# t5 vss u17 vss p23 s_ad32 t6 n/c u18 vcc15 p24 s_ad33 t7 vss u19 vss p25 vss t8 n/c u20 vcc33 p26 s_ad54 t9 vcc15 u21 a18 p27 s_ad55 t10 vss u22 ad14 p28 vss t11 vcc15 u23 vss p29 s_ad56 t12 vss u24 ad12 r1 p_ad63 t13 vcc15 u25 s_gnt3# r2 p_par64 t14 vss u26 vcc33 r3 vcc33 t15 vcc15 u27 s_inta# r4 n/c t16 vss u28 s_intb# table 17. 829-lead package - alphabetical ball listings (sheet 4 of 7) ball signal ball signal ball signal
intel? 80331 i/o processor datasheet package information 42 august 2005 document number: 273943-004US u29 s_ad48 w12 vcc13 y24 ad11 v1 p_rcomp w13 vss y25 a0 v2 p_intd# w14 vcc15 y26 vcc33 v3 vcc33 w15 vss y27 a17 v4 p_intc# w16 vcc15 y28 a21 v5 p_intb# w17 vss y29 a20 v6 vss w18 vcc15 aa1 n/c v7 n/c w19 vss aa2 n/c v8 n/c w20 vcc33 aa3 vss v9 vcc15 w21 a2 aa4 n/c v10 vss w22 a22 aa5 trst# v11 vcc15 w23 ad7 aa6 vss v12 vss w24 ad2 aa7 p_rst# v13 vcc13 w25 vss aa8 hpi# v14 vss w26 ad8 aa9 vss v15 vcc15 w27 ad9 aa10 vcc25/18 v16 vss w28 vss aa11 vss v17 vcc15 w29 a16 aa12 vcc25/18 v18 vss y1 vcc15 aa13 vss v19 vcc15 y2 tck aa14 vcc25/18 v20 vss y3 vss aa15 vss v21 poe# y4 vss aa16 vcc25/18 v22 a19 y5 n/c aa17 vss v23 ad3 y6 tdi aa18 vcc25/18 v24 vcc33 y7 vss aa19 vss v25 ad13 y8 n/c aa20 vcc25/18 v26 ad5 y9 vcc13 aa21 gpio2/u0_cts# v27 vss y10 vss aa22 gpio3/u0_rts# v28 ad1 y11 vcc13 aa23 scl0 v29 ad0 y12 vss aa24 vcc33 w1 pwrdelay y13 vcc13 aa25 pce1# w2 vss y14 vss aa26 pce0# w3 p_inta# y15 vcc15 aa27 vss w4 vss y16 vss aa28 ale w5 vcc33 y17 vcc15 aa29 a1 w6 n/c y18 vss ab1 n/c w7 n/c y19 vcc15 ab2 vss w8 n/c y20 vss ab3 tdo w9 vss y21 pwe# ab4 tms w10 vcc13 y22 ad15 ab5 vss w11 vss y23 vss ab6 vss table 17. 829-lead package - alphabetical ball listings (sheet 5 of 7) ball signal ball signal ball signal
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 43 ab7 vcc25/18 ac19 ras# ae2 vss ab8 vss ac20 vcc25/18 ae3 dqs0# ab9 vcc25/18 ac21 cas# ae4 dqs0 ab10 vss ac22 odt0 ae5 vss ab11 vcc25/18 ac23 vss ae6 dq13 ab12 vss ac24 scd1 ae7 dq8 ab13 vcc25/18 ac25 gpio5/u1_txd ae8 vss ab14 vss ac26 gpio4/u1_rxd ae9 dqs2# ab15 vcc25/18 ac27 ddrcres0 ae10 dq23 ab16 vss ac28 ddrslwcres ae11 vss ab17 vcc25/18 ac29 ddrimpcres ae12 ma1 ab18 vss ad1 dq5 ae13 dq26 ab19 vcc25/18 ad2 dq4 ae14 vss ab20 odt1 ad3 vss ae15 cb0 ab21 scd0 ad4 dq1 ae16 vss ab22 scl1 ad5 dq0 ae17 cb7 ab23 gpio6/u1_cts# ad6 vcc25/18 ae18 dq33 ab24 gpio7/u1_rts# ad7 ma7 ae19 vss ab25 vss ad8 dq12 ae20 cs0# ab26 gpio0/u0_rxd ad9 vss ae21 dm5 ab27 gpio1/u0_txd ad10 dq22 ae22 vss ab28 ddrres1 ad11 dq19 ae23 dq53 ab29 ddrres2 ad12 vcc25/18 ae24 dq52 ac1 ddr_vref ad13 ba1 ae25 vss ac2 vss ad14 dq27 ae26 dq57 ac3 vss ad15 vss ae27 dm7 ac4 vss ad16 cb6 ae28 vss ac5 vss ad17 cb2 ae29 dqs7 ac6 vss ad18 ba0 af1 dq6 ac7 vss ad19 vcc25/18 af2 dq7 ac8 ma11 ad20 we# af3 dq2 ac9 ma9 ad21 vss af4 vcc25/18 ac10 vcc25/18 ad22 ma13 af5 ma12 ac11 vss ad23 cs1# af6 dq9 ac12 ma2 ad24 vcc25/18 af7 vss ac13 ma0 ad25 dq62 af8 dq21 ac14 cb5 ad26 dq63 af9 dqs2 ac15 cb4 ad27 vss af10 vcc25/18 ac16 cb3 ad28 dq59 af11 ma3 ac17 vss ad29 dq58 af12 dq29 ac18 ma10 ae1 dm0 af13 vcc25/18 table 17. 829-lead package - alphabetical ball listings (sheet 6 of 7) ball signal ball signal ball signal
intel? 80331 i/o processor datasheet package information 44 august 2005 document number: 273943-004US af14 dq30 ag26 dq50 aj9 dm2 af15 cb1 ag27 dq51 aj10 ma8 af16 dqs8# ag28 dq60 aj11 dq28 af17 vcc25/18 ag29 vss aj12 dq25 af18 dq32 ah1 -- aj13 dm3 af19 dqs4 ah2 vss aj14 m_ck1 af20 vcc25/18 ah3 m_rst# aj15 m_ck1# af21 dq45 ah4 cke1 aj16 m_ck0 af22 vcc25/18 ah5 vss aj17 m_ck0# af23 dq43 ah6 dq14 aj18 dq36 af24 dq48 ah7 dq20 aj19 dm4 af25 dq49 ah8 vss aj20 dq38 af26 vcc25/18 ah9 ma6 aj21 dq35 af27 dq61 ah10 ma5 aj22 dq40 af28 dq56 ah11 vcc25/18 aj23 dqs5# af29 dqs7# ah12 dq24 aj24 dq46 ag1 vss ah13 dqs3# aj25 dqs6# ag2 dq3 ah14 vss aj26 dqs6 ag3 vss ah15 dm8 aj27 vss ag4 cke0 ah16 vcc25/18 aj28 -- ag5 dm1 ah17 m_ck2 aj29 -- ag6 vss ah18 dq37 ag7 dq11 ah19 vss ag8 dq16ah20dq39 ag9 vss ah21 dq44 ag10 dq18 ah22 vss ag11 ma4 ah23 dqs5 ag12 vss ah24 dq47 ag13 dqs3 ah25 vss ag14 dq31 ah26 dq54 ag15 vss ah27 dq55 ag16 dqs8 ah28 vss ag17 m_ck2# ah29 -- ag18 vss aj1 -- ag19 dqs4# aj2 -- ag20 dq34 aj3 vcc25/18 ag21 vss aj4 dqs1# ag22 dq41 aj5 dqs1 ag23 dq42 aj6 dq15 ag24 vss aj7 dq10 ag25 dm6 aj8 dq17 table 17. 829-lead package - alphabetical ball listings (sheet 7 of 7) ball signal ball signal ball signal
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 45 table 18. 829-lead package - alphabetical signal listings (sheet 1 of 7) signal ball signal ball signal ball -- a1 cas# ac21 dq20 ah7 -- a2 cb0 ae15 dq21 af8 -- a28 cb1 af15 dq22 ad10 -- a29 cb2 ad17 dq23 ae10 -- ah1 cb3 ac16 dq24 ah12 -- ah29 cb4 ac15 dq25 aj12 -- aj1 cb5 ac14 dq26 ae13 -- aj2 cb6 ad16 dq27 ad14 -- aj28 cb7 ae17 dq28 aj11 -- aj29 cke0 ag4 dq29 af12 -- b1 cke1 ah4 dq3 ag2 -- b29 cs0# ae20 dq30 af14 a0 y25 cs1# ad23 dq31 ag14 a1 aa29 ddr_vref ac1 dq32 af18 a16 w29 ddrcres0 ac27 dq33 ae18 a17 y27 ddrimpcres ac29 dq34 ag20 a18 u21 ddrres1 ab28 dq35 aj21 a19 v22 ddrres2 ab29 dq36 aj18 a2 w21 ddrslwcres ac28 dq37 ah18 a20 y29 dm0 ae1 dq38 aj20 a21 y28 dm1 ag5 dq39 ah20 a22 w22 dm2 aj9 dq4 ad2 ad0 v29 dm3 aj13dq40aj22 ad1 v28 dm4 aj19 dq41 ag22 ad10 t21 dm5 ae21 dq42 ag23 ad11 y24 dm6 ag25 dq43 af23 ad12 u24 dm7 ae27 dq44 ah21 ad13 v25 dm8 ah15 dq45 af21 ad14 u22 dq0 ad5 dq46 aj24 ad15 y22 dq1 ad4 dq47 ah24 ad2 w24 dq10 aj7 dq48 af24 ad3 v23 dq11 ag7 dq49 af25 ad4 t23 dq12 ad8 dq5 ad1 ad5 v26 dq13 ae6 dq50 ag26 ad6 t22 dq14 ah6 dq51 ag27 ad7 w23 dq15 aj6 dq52 ae24 ad8 w26 dq16 ag8 dq53 ae23 ad9 w27 dq17 aj8 dq54 ah26 ale aa28 dq18 ag10 dq55 ah27 ba0 ad18dq19ad11dq56af28 ba1 ad13 dq2 af3 dq57 ae26
intel? 80331 i/o processor datasheet package information 46 august 2005 document number: 273943-004US dq58 ad29 m_ck2 ah17 n/c d19 dq59 ad28 m_ck2# ag17 n/c e12 dq6 af1 m_rst# ah3 n/c e13 dq60 ag28 ma0 ac13 n/c e15 dq61 af27 ma1 ae12 n/c e17 dq62 ad25 ma10 ac18 n/c e18 dq63 ad26 ma11 ac8 n/c e7 dq7 af2 ma12 af5 n/c f11 dq8 ae7 ma13 ad22 n/c f13 dq9 af6 ma2 ac12 n/c f14 dqs0 ae4 ma3 af11 n/c f16 dqs0# ae3 ma4 ag11 n/c f17 dqs1 aj5 ma5 ah10 n/c f7 dqs1# aj4 ma6 ah9 p_gnt# g12 dqs2 af9 ma7 ad7 n/c g14 dqs2# ae9 ma8 aj10 n/c g16 dqs3 ag13 ma9 ac9 p_req# h11 dqs3# ah13 n/c a11 n/c h12 dqs4 af19 n/c a12 n/c h13 dqs4# ag19 n/c a18 n/c h7 dqs5 ah23 n/c a19 n/c h8 dqs5# aj23 n/c a20 n/c h9 dqs6 aj26 n/c aa1 n/c j8 dqs6# aj25 n/c aa2 n/c k2 dqs7 ae29 n/c aa4 n/c k5 dqs7# af29 n/c ab1 n/c k6 dqs8 ag16 n/c b12 n/c r25 dqs8# af16 n/c b17 n/c t1 gpio0/u0_rxd ab26 n/c b18 n/c t4 gpio1/u0_txd ab27 n/c c11 n/c t8 gpio2/u0_cts# aa21 n/c c12 n/c u5 gpio3/u0_rts# aa22 n/c c14 n/c u6 gpio4/u1_rxd ac26 n/c c16 n/c u8 gpio5/u1_txd ac25 n/c c17 n/c v7 gpio6/u1_cts# ab23 n/c c19 n/c v8 gpio7/u1_rts# ab24 n/c d11 n/c w6 hpi# aa8 n/c d12 n/c w7 m_ck0 aj16 n/c d14 n/c w8 m_ck0# aj17 n/c d15 n/c y5 m_ck1 aj14 n/c d16 n/c y8 m_ck1# aj15 n/c d18 odt0 ac22 table 18. 829-lead package - alphabetical signal listings (sheet 2 of 7) signalballsignalballsignalball
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 47 odt1 ab20 p_ad45 r5 p_intd# v2 p_ack64# h6 p_ad46 r7 p_irdy# f5 p_ad0 h1 p_ad47 r8 pu1 j7 p_ad1 h3 p_ad48 j2 p_m66en e3 p_ad10 d1 p_ad49 j1 p_par c4 p_ad11 d2 p_ad5 g3 p_par64 r2 p_ad12 d3 p_ad50 k1 p_perr# j4 p_ad13 c2 p_ad51 l4 p_rcomp v1 p_ad14 c3 p_ad52 l3 n/c t6 p_ad15 b3 p_ad53 l1 p_req64# g11 p_ad16 a4 p_ad54 m4 p_rst# aa7 p_ad17 c5 p_ad55 m2 p_serr# j5 p_ad18 a5 p_ad56 m1 p_stop# g6 p_ad19 d6 p_ad57 n3 p_trdy# h10 p_ad2 h4 p_ad58 n2 pce0# aa26 p_ad20 b6 p_ad59 n1 pce1# aa25 p_ad21 a6 p_ad6 f1 poe# v21 p_ad22 c7 p_ad60 p1 pwe# y21 p_ad23 b7 p_ad61 p3 pwrdelay w1 p_ad24 d8 p_ad62 p4 ras# ac19 p_ad25 c8 p_ad63 r1 s_ack64# j28 p_ad26 a8 p_ad7 f2 s_ad0 e24 p_ad27 d9 p_ad8 f4 s_ad1 f23 p_ad28 b9 p_ad9 e4 s_ad10 e20 p_ad29 a9 p_c/be0# e1 s_ad11 h19 p_ad3 g1 p_c/be1# b4 s_ad12 g19 p_ad30 c10 p_c/be2# d5 s_ad13 f19 p_ad31 b10 p_c/be3# a7 s_ad14 h18 p_ad32 k8 p_c/be4# u1 s_ad15 g18 p_ad33 l8 p_c/be5# u2 s_ad16 b27 p_ad34 l7 p_c/be6# t3 s_ad17 c26 p_ad35 l6 p_c/be7# u3 s_ad18 b26 p_ad36 m8 p_clk g9 s_ad19 a26 p_ad37 m7 p_devsel# g5 s_ad2 e23 p_ad38 m5 p_frame# e6 s_ad20 d25 p_ad39 n8 n/c r4 s_ad21 c25 p_ad4 g2 p_idsel k3 s_ad22 a25 p_ad40 n6 p_inta# w3 s_ad23 d24 p_ad41 n5 p_intb# v5 s_ad24 a24 p_ad42 p8 p_intc# v4 s_ad25 c23 p_ad43 p7 p_ad45 r5 s_ad26 b23 table 18. 829-lead package - alphabetical signal listings (sheet 3 of 7) signal ball signal ball signal ball
intel? 80331 i/o processor datasheet package information 48 august 2005 document number: 273943-004US s_ad27 d22 s_ad7 g21 s_serr# e26 s_ad28 c22 s_ad8 d21 s_stop# d28 s_ad29 a22 s_ad9 f20 s_trdy# e28 s_ad3 h22 s_c/be0# h20 scd0 ab21 s_ad30 b21 s_c/be1# h17 scd1 ac24 s_ad31 a21 s_c/be2# c27 scl0 aa23 s_ad32 p23 s_c/be3# d27 scl1 ab22 s_ad33 p24 s_c/be4# k27 tck y2 s_ad34 n24 s_c/be5# k28 tdi y6 s_ad35 n22 s_c/be6# l26 tdo ab3 s_ad36 m25 s_c/be7# l27 tms ab4 s_ad37 m23 s_clkin g27 trst# aa5 s_ad38 m22 s_clko0 h24 vcc13 u12 s_ad39 l23 s_clko1 g24 vcc13 v13 s_ad4 g22 s_clko2 f25 vcc13 w10 s_ad40 l24 s_clko3 h23 vcc13 w12 s_ad41 l22 s_clkout g25 vcc13 y11 s_ad42 k22 s_devsel# f29 vcc13 y13 s_ad43 k24 s_frame# c28 vcc13 y9 s_ad44 j26 s_gnt0# a23 vcc15 a13 s_ad45 j25 s_gnt1# b24 vcc15 a15 s_ad46 j23 s_gnt2# p22 vcc15 c13 s_ad47 j22 s_gnt3# u25 vcc15 c18 s_ad48 u29 s_inta# u27 vcc15 e14 s_ad49 t26 s_intb# u28 vcc15 e16 s_ad5 f22 s_intc# t24 vcc15 h15 s_ad50 t27 s_intd# r23 vcc15 j10 s_ad51 r26 s_irdy# e29 vcc15 j12 s_ad52 r28 pu2 e27 vcc15 j14 s_ad53 r29 s_m66en c20 vcc15 j16 s_ad54 p26 s_par f26 vcc15 k10 s_ad55 p27 s_par64 k29 vcc15 k11 s_ad56 p29 s_pcixcap r21 vcc15 k13 s_ad57 n28 s_perr# g29 vcc15 k9 s_ad58 n29 s_rcomp t29 vcc15 l10 s_ad59 n27 s_req0# n25 vcc15 l12 s_ad6 h21 s_req1# f28 vcc15 l18 s_ad60 m29 s_req2# e21 vcc15 m13 s_ad61 m28 s_req3# k25 vcc15 m15 s_ad62 m26 s_req64# j29 vcc15 m17 s_ad63 l29 s_rst# r22 vcc15 m9 table 18. 829-lead package - alphabetical signal listings (sheet 4 of 7) signalballsignalballsignalball
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 49 vcc15 n10 vcc25/18 aa20 vcc33 j18 vcc15 n12 vcc25/18 ab11 vcc33 j20 vcc15 n14 vcc25/18 ab13 vcc33 j24 vcc15 n16 vcc25/18 ab15 vcc33 j27 vcc15 n18 vcc25/18 ab17 vcc33 j3 vcc15 p11 vcc25/18 ab19 vcc33 k17 vcc15 p15 vcc25/18 ab7 vcc33 k19 vcc15 p17 vcc25/18 ab9 vcc33 k21 vcc15 p19 vcc25/18 ac10 vcc33 l20 vcc15 p9 vcc25/18 ac20 vcc33 l25 vcc15 r10 vcc25/18 ad12 vcc33 l5 vcc15 r12 vcc25/18 ad19 vcc33 m21 vcc15 r14 vcc25/18 ad24 vcc33 m27 vcc15 r18 vcc25/18 ad6 vcc33 m3 vcc15 t11 vcc25/18 af10 vcc33 m6 vcc15 t13 vcc25/18 af13 vcc33 n20 vcc15 t15 vcc25/18 af17 vcc33 n23 vcc15 t17 vcc25/18 af20 vcc33 n26 vcc15 t19 vcc25/18 af22 vcc33 p21 vcc15 t9 vcc25/18 af26 vcc33 r20 vcc15 u10 vcc25/18 af4 vcc33 r24 vcc15 u14 vcc25/18 ah11 vcc33 r27 vcc15 u16 vcc25/18 ah16 vcc33 r3 vcc15 u18 vcc25/18 aj3 vcc33 r6 vcc15 v11 vcc33 aa24 vcc33 u20 vcc15 v15 vcc33 c1 vcc33 u26 vcc15 v17 vcc33 c21 vcc33 u7 vcc15 v19 vcc33 c24 vcc33 v24 vcc15 v9 vcc33 c29 vcc33 v3 vcc15 w14 vcc33 c6 vcc33 w20 vcc15 w16 vcc33 c9 vcc33 w5 vcc15 w18 vcc33 d26 vcc33 y26 vcc15 y1 vcc33 d4 vccpll1 m19 vcc15 y15 vcc33 e9 vccpll2 m11 vcc15 y17 vcc33 f21 vccpll4 r15 vcc15 y19 vcc33 f3 vccpll5 p13 vcc25/18 aa10 vcc33 f6 vss a10 vcc25/18 aa12 vcc33 g10 vss a14 vcc25/18 aa14 vcc33 g23 vss a16 vcc25/18 aa16 vcc33 h26 vss a17 vcc25/18 aa18 vcc33 h5 vss a27 table 18. 829-lead package - alphabetical signal listings (sheet 5 of 7) signal ball signal ball signal ball
intel? 80331 i/o processor datasheet package information 50 august 2005 document number: 273943-004US vss a3 vss ae28 vss d23 vss aa11 vss ae5 vss d29 vss aa13 vss ae8 vss d7 vss aa15 vss af7 vss e10 vss aa17 vss ag1 vss e11 vss aa19 vss ag12 vss e19 vss aa27 vss ag15 vss e2 vss aa3 vss ag18 vss e22 vss aa6 vss ag21 vss e25 vss aa9 vss ag24 vss e5 vss ab10 vss ag29 vss e8 vss ab12 vss ag3 vss f10 vss ab14 vss ag6 vss f12 vss ab16 vss ag9 vss f15 vss ab18 vss ah14 vss f18 vss ab2 vss ah19 vss f24 vss ab25 vss ah2 vss f27 vss ab5 vss ah22 vss f8 vss ab6 vss ah25 vss f9 vss ab8 vss ah28 vss g13 vss ac11 vss ah5 vss g15 vss ac17 vss ah8 vss g17 vss ac2 vss aj27 vss g20 vss ac23 vss b11 vss g26 vss ac3 vss b13 vss g28 vss ac4 vss b14 vss g4 vss ac5 vss b15 vss g7 vss ac6 vss b16 vss g8 vss ac7 vss b19 vss h14 vss ad15 vss b2 vss h16 vss ad21 vss b20 vss h2 vss ad27 vss b22 vss h25 vss ad3 vss b25 vss h27 vss ad9 vss b28 vss h28 vss ae11 vss b5 vss h29 vss ae14 vss b8 vss j11 vss ae16 vss c15 vss j13 vss ae19 vss d10 vss j15 vss ae2 vss d13 vss j17 vss ae22 vss d17 vss j19 vss ae25 vss d20 vss j21 table 18. 829-lead package - alphabetical signal listings (sheet 6 of 7) signalballsignalballsignalball
intel? 80331 i/o processor datasheet package information document number: 273943-004US august 2005 51 vss j6 vss p2 vss w19 vss j9 vss p20 vss w2 vss k12 vss p25 vss w25 vss k14 vss p28 vss w28 vss k15 vss p5 vss w4 vss k16 vss r11 vss w9 vss k18 vss r13 vss y10 vss k20 vss r17 vss y12 vss k23 vss r19 vss y14 vss k26 vss r9 vss y16 vss k4 vss t10 vss y18 vss k7 vss t12 vss y20 vss l11 vss t14 vss y23 vss l13 vss t16 vss y3 vss l14 vss t18 vss y4 vss l15 vss t2 vss y7 vss l16 vss t20 vssa1 m18 vss l17 vss t25 vssa2 m12 vss l19 vss t28 vssa4 r16 vss l2 vss t5 vssa5 p14 vss l21 vss t7 we# ad20 vss l28 vss u11 vss l9 vss u13 vss m10 vss u15 vss m14 vss u17 vss m16 vss u19 vss m20 vss u23 vss m24 vss u4 vss n11 vss u9 vss n13 vss v10 vss n15 vss v12 vss n17 vss v14 vss n19 vss v16 vss n21 vss v18 vss n4 vss v20 vss n7 vss v27 vss n9 vss v6 vss p10 vss w11 vss p12 vss w13 vss p16 vss w15 vss p18 vss w17 table 18. 829-lead package - alphabetical signal listings (sheet 7 of 7) signal ball signal ball signal ball
intel? 80331 i/o processor datasheet package information 52 august 2005 document number: 273943-004US 3.2 package thermal specifications see intel ? 80331 i/o processor thermal design guidelines application note (273980).
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 53 4.0 electrical specifications 4.1 absolute maximum ratings 4.2 v ccpll pin requirements the v ccpll[1-5] balls for the phase lock loop (pll) circuit must each have filters, and be connected to the appropriate vssa ball. see the intel ? 80331 i/o processor design guide for specific recommendations. note: there are no vccpll3 or vssa3 signals. table 19. absolute maximum ratings parameter maximum rating note: this data sheet contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product becomes available. the specifications are subject to change without notice. contact your local intel representative before finalizing a design. storage temperature ?55 c to +125c case temperature under bias 0c to +95c supply voltage v cc33 wrt. v ss ?0.5 v to +4.1 v supply voltage v cc25 wrt. v ss ?0.5 v to +3.2 v supply voltage v cc15 wrt. v ss ?0.5 v to +2.1 v supply voltage v cc13 wrt. v ss ?0.5 v to +2.1 v voltage on any ball wrt. v ss ?0.5 v to v ccp + 0.5 v warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 20. operating conditions symbol parameter minimum maximum units notes v cc33 3.3 v pci/pci-x supply voltage 3.0 3.6 v +/- 10% v cc25/18 2.5 v/1.8v ddr/ddr-ii supply voltage 2.3/1.7 2.7/1.9 v +/-8%, 5% 1 1. +/- 3% dc; additional +/- 2% for ac transients. under no circumstance may the supply voltage go past the ac min/max window. the supply voltage window may go outside the dc min/max window for transient events. v cc15 1.5 v iop core supply voltage 1.425 1.575 v +/- 5% 1 v cc13 1.35 v intel xscale ? core supply voltage 1.282 1.418 v +/- 5% v ccpll1-5 pll supply voltage v cc15 v cc15 v ddr_vref memory i/o reference voltage 0.49 v cc25/18 0.51 v cc25/18 v p_clk input clock frequency 16 133 mhz t c case temperature under bias 0 95 c
intel? 80331 i/o processor datasheet electrical specifications 54 august 2005 document number: 273943-004US 4.3 targeted dc specifications table 21. dc characteristics symbol parameter minimum maximum units notes v il1 input low voltage (ddr sdram) -0.3 ddr_vref - 0.18 v ( 1 , 2 ) v ih1 input high voltage (ddr sdram) ddr_vref + 0.18 v cc25 + 0.3 v ( 1 , 2 ) v il2 input low voltage (ddr-ii sdram) -0.2 ddr_vref - 0.125 v ( 1 , 3 ) v ih2 input high voltage (ddr-ii sdram) ddr_vref + 0.125 v cc25 + 0.2 v ( 1 , 3 ) v il2 input low voltage (misc.) -0.3 0.8 v ( 4 ) v ih2 input high voltage (misc.) 2.0 v cc33 + 0.3 v ( 4 ) v il3 input low voltage (pci-x) -0.5 0.35 v cc33 v v ih3 input high voltage (pci-x/pci) 0.5 v cc33 v cc33 + 0.5 v v il5 input low voltage (pci) -0.5 0.3 v cc33 v v ol2 output low voltage (misc.) 0.4 v i ol = 6 ma v oh2 output high voltage (misc.) 2.4 v i oh = -2 ma v ol1 output low voltage (ddr sdram) 0.35 v i ol = 12.5 ma ( 1 , 2 ) v oh1 output high voltage (ddr sdram) 1.95 v i oh = -12.5 ma ( 1 , 2 ) v ol2 output low voltage (ddr-ii sdram) 0.414 v i ol = 20.7ma ( 3 ) v oh2 output high voltage (ddr-ii sdram) 1.314 v i oh = -18ma ( 3 ) v ol3 output low voltage (pci-x) 0.1 v cc33 v i ol = 1500 a v oh3 output high voltage (pci-x) 0.9 v cc33 v i oh = -500 a c in input pin capacitance 8 pf ( 5 ) c clk pci clock pin capacitance 8 pf ( 5 ) l pin ball inductance 15 nh ( 1 , 2 , 5 ) notes: 1. sdram signals include ma[12:0] , ba[1:0] , cas# , cs[1:0]# , cke[1:0] , dm[8:0] , ras# , we# , m_ck[2:0] , m_ck[2:0]# , dq[63:0] , dqs[8:0] and cb[7:0] . 2. for 2.5 v ddr sdram support. 3. for 1.8 v ddr-ii sdram support. 4. miscellaneous signals include all signals that are not pci-x or sdram signals. 5. ensured by design.
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 55 table 22. i cc characteristics symbol parameter typ max units notes i li1 input leakage current for each signal except tck , tms , trst# , tdi 2 a 0 v in v cc (4) i li2 input leakage current for tck , tms , trst# , tdi -140 -250 a v in = 0.45 v ( 1 , 4) i cc33 active (power supply) power supply current - pci-x interfaces both at 66 mhz both at 100 mhz both at 133 mhz 1.33 1.20 1.04 a ( 1 , 2 ) i cc25 active (power supply) power supply current - ddr 0.580 a ( 1 , 2 ) i cc18 active (power supply) power supply current - ddr-ii 0.487 a ( 1 , 2 ) i cc15 active (power supply) power supply current - iop/bridge core 3.2 a ( 1 , 2 ) i cc13 active (power supply) power supply current - intel xscale ? core 800 mhz 667 mhz 500 mhz 0.453 0.411 0.358 a ( 1 , 2 ) i cc33 active (thermal) thermal current - pci-x interfaces both at 66 mhz both at 100 mhz both at 133 mhz 1.08 1.00 0.914 a ( 1 , 3 ) i cc25 active (thermal) thermal current - ddr 0.295 a ( 1 , 3 ) i cc18 active (thermal) thermal current - ddr-ii 0.255 a ( 1 , 3 ) i cc15 active (thermal) thermal current - iop/bridge core 2.5 a ( 1 , 3 ) i cc13 active (thermal) thermal current - intel xscale ? core 800 mhz 667 mhz 500 mhz 0.430 0.390 0.340 a ( 1 , 3 ) notes: 1. measured with device operating and outputs loaded to the test condition in figure 14 ?ac test load for all signals except pci and ddr sdram? on page 67 . 2. i cc active (power supply) value is provided for select ing the system power suppl y. this is based on the worst case data patterns and skew material at the following worst case voltages: v cc33 = 3.63 v, v cc25 = 2.7 v, v cc18 = 1.9v, v cc15 = 1.575 v, v cc13 = 1.41 v. 3. i cc active (thermal) value is provided for selecting the system thermal design power (tdp). this is based on the following typical voltages: v cc33 = 3.3 v, v cc25 = 2.5 v, v cc18 = 1.8v, v cc15 = 1.5 v, v cc13 = 1.35 v. 4. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs.
intel? 80331 i/o processor datasheet electrical specifications 56 august 2005 document number: 273943-004US 4.4 targeted ac specifications 4.4.1 clock signal timings table 23. pci clock timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max min. max min. max min. max min. max t f1 pci clock frequency 100 133 66 100 50 66 33 66 16 33 mhz 1 t c1 pci clock cycle time - avg. absolute minimum 7.5101015152015303060 ns 1 7.375 9.875 14.8 14.8 29.7 ns 3 , 4 t ch1 pci clock high time 3 3 6 6 11 ns t cl1 pci clock low time 3 3 6 6 11 ns t sr1 pci clock slew rate 1.5 4 1.5 4 1.5 4 1.5 4 1 4 v/ns 2 pci spread spectrum requirements f mod pci clock modulation frequency 30 33 30 33 30 33 30 33 khz f spread pci clock frequency spread -1 0 -1 0 -1 0 -1 0 % notes: 1. clock frequency may not change beyond spread-spectrum limits except while is asserted. 2. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. the minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 4. clock jitter class 2, per pci-x electrical and mechanical rev 2.0a specification table 24. ddr clock timings symbol parameter ddr-ii 400 ddr333 units notes minimum maximum minimum maximum t f2 ddr sdram clock frequency 200 167 mhz t c2 ddr sdram clock cycle time 5.0 6.0/7.5 (1) ns t ch2 ddr sdram clock high time 2.15 2.7/3.37 (1) ns t cl2 ddr sdram clock lowtime 2.15 2.7/3.37 (1) ns t cs2 ddr sdram clock period stability 350 350 ps t skew2 ddr sdram clock skew for any differential clock pair ( m_ck[2:0] - m_ck[2:0]# ) 100 100 ps t skew3 ddr sdram clock skew for any clock pair and any system memory strobe ( m_ck - dqs ). -285 285 -285 285 ps 2 notes: 1. cl = 2.5/2.0. 2. this specification applies for writes only; that is, when the 80331 is driving the strobes as well as the clocks. refer to th e jedec specification for an explanation of strobe to clock timing for ddr reads.
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 57 4.4.2 ddr/ddr-ii sdram interface signal timings table 25. ddr sdram signal timings symbol parameter minimum max. units notes t vb1 dq, cb and dm write output valid time before dqs. 2.68 ns ( 4 ) t va1 dq, cb and dm write output valid time after dqs. 2.68 ns ( 4 ) t vb3 address and command write output valid before m_ck rising edge. 2.62 ns ( 4 , 8 ) t va3 address and command write output valid after m_ck rising edge. 2.62 ns ( 4 , 8 ) t vb4 dq, cb and dm read input valid time before dqs rising or falling edges. 0.35 ns ( 5 ) t va4 dq, cb and dm read input valid time after dqs rising or falling edges. 0.35 ns ( 5 ) t vb5 cs[1:0]# control valid before m_ck rising edge. 2.62 ns ( 4 ) t va5 cs[1:0]# control valid after m_ck rising edge. 2.62 ns ( 4 ) t vb6 dqs write preamble duration. 4.50 (nominal) ns ( 6 ) t va6 dqs write postamble duration. 3.00 (nominal) ns ( 6 ) notes: 1. see figure 7 ?output timing measurement waveforms? on page 63 . 2. see figure 8 ?input timing measurement waveforms? on page 64 . 3. clock to output valid times are specified with a 0 pf loading. 4. see figure 11 ?ddr sdram write timings? on page 65 . 5. see figure 12 ?ddr sdram read timings? on page 65 . 6. see figure 13 ?write preamble/postamble durations? on page 66 . 7. see figure 15 ?ac test load for ddr sdram signals? on page 67 . 8. address/command pin group; ras# , cas# , we# , ma[12:0] , ba[1:0] .
intel? 80331 i/o processor datasheet electrical specifications 58 august 2005 document number: 273943-004US table 26. ddr-ii sdram signal timings symbol parameter mini max units notes t vb1 dq, cb and dm write output valid time before dqs crossing. 2.12 ns 4 t va1 dq, cb and dm write output valid time after dqs crossing. 2.12 ns 4 t vb3 address and command write output valid before m_ck rising edge 2.12 ns 4 t va3 address and command write output valid after m_ck rising edge 2.12 ns 4 , 8 t vb4 dq, cb and dm read input valid time before dqs rising or falling edges 0.35 ns 6 t va4 dq, cb and dm read input valid time after dqs rising or falling edges 0.35 ns 6 t vb5 cs[1:0]# control valid before m_ck rising edge. 2.12 ns 4 t va5 cs[1:0]# control valid after m_ck rising edge. 2.12 ns 4 t vb6 dqs write preamble duration. 3.75 (nom) ns 9 t va6 dqs write postamble duration. 2.50 (nom) ns 9 notes: 1. see figure 7 ?output timing measurement waveforms? on page 63 . 2. see figure 8 ?input timing measurement waveforms? on page 64 . 3. clock to output valid times are specified with a 0 pf loading. 4. see figure 11 ?ddr sdram write timings? on page 65 . 5. see figure 13 ?dqs falling edge output access time to m_ck rising edge. 6. see figure 12 ?ddr sdram read timings? on page 65 . data to strobe read setup and data from strobe read hold minimum requirements specified are det ermined with the dqs delay programmed for a 90 degree phase shift. 7. see figure 15 ?ac test load for ddr sdram signals? on page 67 . 8. address/command pin group: ras#, cas#, we#, ma[12:0], ba[1:0], odt[1:0] . 9. see figure 13 ?write preamble/postamble durations? on page 66 .
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 59 4.4.3 peripheral bus interface signal timings table 27. peripheral bus signal timings symbol parameter min max units notes t ov1 output valid delay from m_ck 1 5 ns ( 1 , 3 ) t of output float delay from m_ck 1 5 ns ( 1 , 3 ) t is1 input setup to m_ck 4.5 ns ( 2 ) t ih1 input hold from m_ck 2 ns ( 2 ) t ah1 ale high time 15 ns t av1 ale high to address valid 0 ns t ah2 ale low to address invalid 15 ns t as1 address valid to ale low 15 ns t ao1 ale low to poe# low 0 ns t aw1 ale low to pwe# low 15 ns t ah3 pwe# high to data invalid 15 ns t as2 data valid to pwe# high 60 ns t ac1 ale low to pce[1:0]# low 15 ns notes: 1. see figure 7 ?output timing measurement waveforms? on page 63 . 2. see figure 8 ?input timing measurement waveforms? on page 64 . 3. see figure 14 ?ac test load for all signals except pci and ddr sdram? on page 67 . 4. see table 32, ac measurement conditions. 5. all timing referenced to m_ck is for functional testing, for the cases where m_ck * n = ibclk. 6. pbi clock is internal only; 66 mhz with 266 mhz internal bus.
intel? 80331 i/o processor datasheet electrical specifications 60 august 2005 document number: 273943-004US table 28. pci signal timings symbol parameter pci-x 133 pci-x 100 pci-x 66 pci 66 pci 33 units notes min. max min. max min. max min. max t ov1 clock to output valid delay for bused signals 0.7 3.8 0.7 3.8 1 6 2 11 ns ( 1 , 2 , 3 ) t ov2 clock to output valid delay for point to point signals 0.7 3.8 0.7 3.8 2 6 2 12 ns ( 1 , 2 , 3 ) t of clock to output float delay 7 7 14 28 ns ( 1 , 7 ) t is1 input setup to clock for bused signals 1.2 1.7 3 7 ns ( 3 , 4 , 8 ) t is2 input setup to clock for point to point signals 1.2 1.7 5 10, 12 ns ( 3 , 4 ) t ih1 input hold time from clock 0.5 0.5 0 0 ns ( 4 ) t rst reset active time 1 1 1 1 ms t rf reset active to output float delay 40 40 40 40 ns ( 5 , 6 ) t is3 req64# to reset setup time 10 10 10 10 clocks t ih2 reset to req64# hold time 0 50 0 50 0 50 0 50 ns t is4 pci-x initialization pattern to reset setup time 10 10 clocks t ih3 reset to pci-x initialization pattern hold time 0500 50 ns notes: 1. see the timing measurement conditions in; figure 7 ?output timing measurement waveforms? on page 63 . 2. see figure 16 ?pci/pci-x tov(max) rising edge ac test load? on page 67 , figure 17 ?pci/pci-x tov(max) falling edge ac test load? on page 68 , and figure 18 ?pci/pci-x tov(min) ac test load? on page 68 . 3. setup time for point-to-point signals applies to req# and gnt # only. all other signals are bused. 4. see the timing measurement conditions in figure 8 ?input timing measurement waveforms? on page 64 . 5. rst# is asserted and deasserted asynchronously with respect to clk. 6. all output drivers must be floated when rst# is active. 7. for purposes of active/float timing measurements, the hi-z or ?off? state is defined to be when the total current delivered through the component pin is less t han or equal to the leakage current specification. 8. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time.
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 61 4.4.4 i 2 c interface signal timings 4.4.5 uart interface signal timings table 29. i 2 c signal timings symbol parameter std. mode fast mode units notes min. max min. max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 1.3 s ( 1 ) t hdsta hold time (repeated) start condition 4 0.6 s ( 1 , 3 ) t low scl clock low time 4.7 1.3 s ( 1 , 2 ) t high scl clock high time 4 0.6 s ( 1 , 2 ) t susta setup time for a repeated start condition 4.7 0.6 s ( 1 ) t hddat data hold time 0 3.45 0 0.9 s ( 1 ) t sudat data setup time 250 100 ns ( 1 ) t sr scl and sda rise time 1000 20+0.1 c b 300 ns ( 1 , 4 ) t sf scl and sda fall time 300 20+0.1 c b 300 ns ( 1 , 4 ) t susto setup time for stop condition 4 0.6 s ( 1 ) notes: 1. see figure 9 ?i2c/smbus interface signal timings? on page 64 . 2. not tested. 3. after this period, the first clock pulse is generated. 4. c b = the total capacitance of one bus line, in pf.i 2 c table 30. uart signal timings symbol parameter std. mode units notes min. max t xd1 ux_txd output delay from m_ck rising edge 60 ns 1 t rxs1 ux_rxd data setup time (to m_ck rising edge). 50 ns t rxh1 ux_rxd data hold time (to m_ck rising edge). 50 ns t cts1 ux_cts setup time (to m_ck rising edge). 60 ns t cth1 ux_cts hold time (to m_ck rising edge). 60 ns t rts1 ux_rts setup time (to m_ck rising edge). 60 ns t rth1 ux_rts hold time (to m_ck rising edge). 60 ns 1. see figure 10 ?uart transmitter receiver timing? on page 64 .
intel? 80331 i/o processor datasheet electrical specifications 62 august 2005 document number: 273943-004US 4.4.6 boundary scan test signal timings table 31. boundary scan test signal timings symbol parameter min. max units notes t bsf tck frequency 0 0.5t f mhz t bsch tck high time 15 ns measured at 1.5 v ( 1 ). t bscl tck low time 15 ns measured at 1.5 v ( 1 ). t bscr tck rise time 5 ns 0.8 v to 2.0 v ( 1 ) t bscf tck fall time 5 ns 2.0 v to 0.8 v ( 1 ) t bsis1 input setup to tck ? tdi , tms 3ns( 4 ) t bsih1 input hold from tck ? tdi , tms 5ns( 4 ) t bsov1 tdo valid delay 5 15 ns relative to falling edge of tck ( 2 , 3 ). t of1 tdo float delay 5 15 ns relative to falling edge of tck ( 2 , 5 ). notes: 1. not tested. 2. outputs precharged to v cc5 . 3. see figure 7 ?output timing measurement waveforms? on page 63 . 4. see figure 8 ?input timing measurement waveforms? on page 64 . 5. a float condition occurs when the output current becomes less than ilo. float delay is not tested. see figure 7 ?output timing measurement waveforms? on page 63 .
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 63 4.5 ac timing waveforms figure 6. clock timing measurement waveforms figure 7. output timing measurement waveforms t cf t cr t ch t cl t c v tch v ih(min) v il(max) v test v tcl v test clk output float v trise output delay rise output delay fall v tfall t ov t ov t of v tl v th
intel? 80331 i/o processor datasheet electrical specifications 64 august 2005 document number: 273943-004US figure 8. input timing measurement waveforms figure 9. i 2 c/smbus interface signal timings figure 10. uart transmitter receiver timing clk input valid v test v test v test t is t ih v tl v th v th v tl v max sda scl t buf stop start t low t hdsta t high t sr t hddat t sf t sudat t susta repeated t hdsta t sp stop t susto start m_ck ux_txd t xd1 ux_rxd t rxh1 t rxs1
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 65 figure 11. ddr sdram write timings figure 12. ddr sdram read timings m_ck dqs dq t va1 t vb1 t vb5 t va5 cs[1:0]# t vb3 t va3 addr/ctrl dqs# dqs dq t vb4 t va4
intel? 80331 i/o processor datasheet electrical specifications 66 august 2005 document number: 273943-004US figure 13. write preamble/postamble durations dqs t vb6 dqs t va6
intel? 80331 i/o processor datasheet electrical specifications document number: 273943-004US august 2005 67 4.6 ac test conditions table 32. ac measurement conditions symbol pci-x pci ddr ddr-ii pbi units v th 0.6 v cc33 0.6 v cc33 2.0 1.15 2.0 v v tl 0.25 v cc33 0.2 v cc33 0.5 0.2 0.8 v v test 0.4 v cc33 0.4 v cc33 1.25 0.90 1.5 v v trise 0.285 v cc33 0.285 v cc33 1.25 0.90 1.5 v v tfall 0.615 v cc33 0.615 v cc33 1.25 0.90 1.5 v v max 0.4 v cc33 0.4 v cc33 1.5 0.97 1.2 v slew rate (1) 1.5 1.5 1.0 1.0 1.0 v/ns 1. input signal slew rate is measured between v il and v ih . figure 14. ac test load for all signals except pci and ddr sdram figure 15. ac test load for ddr sdram signals figure 16. pci/pci-x t ov(max) rising edge ac test load output 50pf te s t point 25 ? 30pf 25 ? 1.25v output te st point output te s t point 10pf 25 ?
intel? 80331 i/o processor datasheet electrical specifications 68 august 2005 document number: 273943-004US figure 17. pci/pci-x t ov(max) falling edge ac test load figure 18. pci/pci-x t ov(min) ac test load output 10pf 25 ? v cc33 te st point output te st point 10pf 1k ? 1k ? v cc33

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